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  1. 20 Aug, 2017 1 commit
    • Adam Nelson's avatar
      Atomic memory cells and operations for WMM/RISC-V · 59737ac5
      Adam Nelson authored
      - Memory and registers are split up into typed atomic cells
      - Value type now contains only scalar values
      - Instructions are compiled down to WMM "operations", allowing stores
        and loads of composite values to be split up into atomic parts
      - Scheduler now executes one operation at a time, rather than one block
        at a time
      - New scheduler steps for WMM
      - Commands (formerly Thread Actions) such as allocation now executed at
        the global scheduler level. Action IDs no longer needed.
      - Threads and stacks changed completely; registers now stored in stack
      - Monads pretty-print properly again!
      - Patricia trees replaced with sptrees
      Lots of code is still commented out, and tests still don't work, but
      the main formalization code compiles.
  2. 25 Jun, 2017 1 commit
    • Adam Nelson's avatar
      More progress on RISC-V, change pop-frame process · b1d3c66c
      Adam Nelson authored
      - Free was changed from a store message to a thread_action message
      - Stack frames are now freed properly when returning from a function
      - Heap/stack addresses are tracked separately again
      - New stores are added to invalidation buffers, per the spec
      - Thread actions are executed now
      - Tests still don't work yet
  3. 06 Jun, 2017 1 commit
  4. 05 May, 2017 1 commit
    • Adam Nelson's avatar
      Prove local seq consistency for seq_cst_schedule · fb68640a
      Adam Nelson authored
      It's finally done! The first memory consistency proof in the formalization:
      a sequentially consistent schedule (one that always commits memory messages
      from the front of a thread's outbox queue) will always produce locally
      sequentially consistent semantics.
      Changes made in the process of this proof include:
      - Removed thread IDs and stack IDs from the thread and stack records;
        keeping up with invariants for them was pointless bookkeeping
      - Defined custom tactics multi_case_tac and rw_assums, which greatly
        reduced the size and complexity of some proofs
      - Added several new invariants to state_ok, including memory consistency
        invariants (committed messages are all distinct, no message can be in
        both the commit list and a thread's outbox, etc.)
  5. 02 Apr, 2017 1 commit
  6. 24 Nov, 2016 1 commit
    • Adam Nelson's avatar
      Redesign with symbolic values (incomplete) · 5fbca740
      Adam Nelson authored
      Thread and memory semantics are being overhauled to use lazy symbolic values,
      making the system similar to the one described in the Nienhuis paper.
      Everything up to uvmThreadSemantics compiles; uvmScheduler is still incomplete.
      Tests currently don't work.
      Changes include:
      - The "symbolic" monad defines lazy computations.
      - Thread semantics execute an entire block at a time.
      - Thread semantics is greatly simplified, with fewer record types, queues, and
        edge cases.
      - Thread semantics does not know anything about the actual values of its
        registers. Branching instructions must receive a "guess" value from the
        scheduler; this value may be a real register value or a branch prediction.
      - There are now only two scheduler step types: Commit (commits a memory message)
        and Proceed (moves a thread to the next block, optionally with a branch
      - Pluggable memory models are gone; concurrency semantics will be handled by an
        extra layer on top of the scheduler.
      - DefineUtils has some shortcuts for defining monads and num wrapper types.
  7. 15 Nov, 2016 1 commit
  8. 16 Jul, 2016 1 commit
    • Adam R. Nelson's avatar
      Make eval'ing UIR code fragments work · fdfff5db
      Adam R. Nelson authored
      This was accomplished by changing the way enter_block works, removing
      the overly-complicated argument passing through simulated ID
      instructions and replacing it with memreq propagation in registers.
      A lot of support code and code/proof cleanup was also added.