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inst_sel.rs 128 KB
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use ast::ir::*;
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use ast::ptr::*;
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use ast::inst::*;
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use ast::op;
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use ast::op::OpCode;
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use ast::types;
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use ast::types::*;
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use vm::VM;
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use runtime::mm;
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use runtime::ValueLocation;
use runtime::thread;
use runtime::entrypoints;
use runtime::entrypoints::RuntimeEntrypoint;
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use compiler::CompilerPass;
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use compiler::backend;
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use compiler::backend::PROLOGUE_BLOCK_NAME;
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use compiler::backend::x86_64;
use compiler::backend::x86_64::CodeGenerator;
use compiler::backend::x86_64::ASMCodeGen;
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use compiler::machine_code::CompiledFunction;
use compiler::frame::Frame;
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use std::collections::HashMap;
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use std::any::Any;
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pub struct InstructionSelection {
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    name: &'static str,
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    backend: Box<CodeGenerator>,
    
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    current_callsite_id: usize,
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    current_frame: Option<Frame>,
    current_block: Option<MuName>,
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    current_func_start: Option<ValueLocation>,
    // key: block id, val: callsite that names the block as exception block
    current_exn_callsites: HashMap<MuID, Vec<ValueLocation>>,
    // key: block id, val: block location
    current_exn_blocks: HashMap<MuID, ValueLocation>     
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}

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impl <'a> InstructionSelection {
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    #[cfg(feature = "aot")]
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    pub fn new() -> InstructionSelection {
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        InstructionSelection{
            name: "Instruction Selection (x64)",
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            backend: Box::new(ASMCodeGen::new()),
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            current_callsite_id: 0,
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            current_frame: None,
            current_block: None,
            current_func_start: None,
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            // key: block id, val: callsite that names the block as exception block
            current_exn_callsites: HashMap::new(), 
            current_exn_blocks: HashMap::new()
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        }
    }
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    #[cfg(feature = "jit")]
    pub fn new() -> InstructionSelection {
        unimplemented!()
    }
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    // in this pass, we assume that
    // 1. all temporaries will use 64bit registers
    // 2. we do not need to backup/restore caller-saved registers
    // 3. we need to backup/restore all the callee-saved registers
    // if any of these assumption breaks, we will need to re-emit the code
    #[allow(unused_variables)]
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    fn instruction_select(&mut self, node: &'a TreeNode, f_content: &FunctionContent, f_context: &mut FunctionContext, vm: &VM) {
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        trace!("instsel on node {}", node);
        
        match node.v {
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            TreeNode_::Instruction(ref inst) => {
                match inst.v {
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                    Instruction_::Branch2{cond, ref true_dest, ref false_dest, true_prob} => {
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                        trace!("instsel on BRANCH2");
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                        // 'branch_if_true' == true, we emit cjmp the same as CmpOp  (je  for EQ, jne for NE)
                        // 'branch_if_true' == false, we emit opposite cjmp as CmpOp (jne for EQ, je  for NE)
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                        let (fallthrough_dest, branch_dest, branch_if_true) = {
                            if true_prob > 0.5f32 {
                                (true_dest, false_dest, false)
                            } else {
                                (false_dest, true_dest, true)
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                            }
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                        };
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                        let ops = inst.ops.read().unwrap();
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                        self.process_dest(&ops, fallthrough_dest, f_content, f_context, vm);
                        self.process_dest(&ops, branch_dest, f_content, f_context, vm);
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                        let branch_target = f_content.get_block(branch_dest.target).name().unwrap();
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                        let ref cond = ops[cond];
                        
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                        if self.match_cmp_res(cond) {
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                            trace!("emit cmp_res-branch2");
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                            match self.emit_cmp_res(cond, f_content, f_context, vm) {
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                                op::CmpOp::EQ => {
                                    if branch_if_true {
                                        self.backend.emit_je(branch_target);
                                    } else {
                                        self.backend.emit_jne(branch_target);
                                    }
                                },
                                op::CmpOp::NE => {
                                    if branch_if_true {
                                        self.backend.emit_jne(branch_target);
                                    } else {
                                        self.backend.emit_je(branch_target);
                                    }
                                },
                                op::CmpOp::UGE => {
                                    if branch_if_true {
                                        self.backend.emit_jae(branch_target);
                                    } else {
                                        self.backend.emit_jb(branch_target);
                                    }
                                },
                                op::CmpOp::UGT => {
                                    if branch_if_true {
                                        self.backend.emit_ja(branch_target);
                                    } else {
                                        self.backend.emit_jbe(branch_target);
                                    }
                                },
                                op::CmpOp::ULE => {
                                    if branch_if_true {
                                        self.backend.emit_jbe(branch_target);
                                    } else {
                                        self.backend.emit_ja(branch_target);
                                    }
                                },
                                op::CmpOp::ULT => {
                                    if branch_if_true {
                                        self.backend.emit_jb(branch_target);
                                    } else {
                                        self.backend.emit_jae(branch_target);
                                    }
                                },
                                op::CmpOp::SGE => {
                                    if branch_if_true {
                                        self.backend.emit_jge(branch_target);
                                    } else {
                                        self.backend.emit_jl(branch_target);
                                    }
                                },
                                op::CmpOp::SGT => {
                                    if branch_if_true {
                                        self.backend.emit_jg(branch_target);
                                    } else {
                                        self.backend.emit_jle(branch_target);
                                    }
                                },
                                op::CmpOp::SLE => {
                                    if branch_if_true {
                                        self.backend.emit_jle(branch_target);
                                    } else {
                                        self.backend.emit_jg(branch_target);
                                    }
                                },
                                op::CmpOp::SLT => {
                                    if branch_if_true {
                                        self.backend.emit_jl(branch_target);
                                    } else {
                                        self.backend.emit_jge(branch_target);
                                    }
                                },
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                                _ => unimplemented!()
                            }
                        } else if self.match_ireg(cond) {
                            trace!("emit ireg-branch2");
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                            let cond_reg = self.emit_ireg(cond, f_content, f_context, vm);
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                            // emit: cmp cond_reg 1
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                            self.backend.emit_cmp_imm_r(1, &cond_reg);
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                            // emit: je #branch_dest
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                            self.backend.emit_je(branch_target);
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                        } else {
                            unimplemented!();
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                        }
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                    },
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                    Instruction_::Select{cond, true_val, false_val} => {
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                        trace!("instsel on SELECT");
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                        let ops = inst.ops.read().unwrap();

                        let ref cond = ops[cond];
                        let ref true_val = ops[true_val];
                        let ref false_val = ops[false_val];

                        if self.match_ireg(true_val) {
                            // moving integers/pointers
                            let tmp_res   = self.get_result_value(node);
                            let tmp_true  = self.emit_ireg(true_val, f_content, f_context, vm);
                            let tmp_false = self.emit_ireg(false_val, f_content, f_context, vm);

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                            // mov tmp_false -> tmp_res
                            self.backend.emit_mov_r_r(&tmp_res, &tmp_false);

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                            if self.match_cmp_res(cond) {
                                match self.emit_cmp_res(cond, f_content, f_context, vm) {
                                    op::CmpOp::EQ => {
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                                        self.backend.emit_cmove_r_r (&tmp_res, &tmp_true);
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                                    }
                                    op::CmpOp::NE => {
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                                        self.backend.emit_cmovne_r_r(&tmp_res, &tmp_true);
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                                    }
                                    op::CmpOp::SGE => {
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                                        self.backend.emit_cmovge_r_r(&tmp_res, &tmp_true);
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                                    }
                                    op::CmpOp::SGT => {
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                                        self.backend.emit_cmovg_r_r (&tmp_res, &tmp_true);
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                                    }
                                    op::CmpOp::SLE => {
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                                        self.backend.emit_cmovle_r_r(&tmp_res, &tmp_true);
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                                    }
                                    op::CmpOp::SLT => {
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                                        self.backend.emit_cmovl_r_r (&tmp_res, &tmp_true);
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                                    }
                                    op::CmpOp::UGE => {
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                                        self.backend.emit_cmovae_r_r(&tmp_res, &tmp_true);
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                                    }
                                    op::CmpOp::UGT => {
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                                        self.backend.emit_cmova_r_r (&tmp_res, &tmp_true);
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                                    }
                                    op::CmpOp::ULE => {
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                                        self.backend.emit_cmovbe_r_r(&tmp_res, &tmp_true);
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                                    }
                                    op::CmpOp::ULT => {
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                                        self.backend.emit_cmovb_r_r (&tmp_res, &tmp_true);
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                                    }
                                    _ => panic!("expecting CmpOp for integers")
                                }
                            } else if self.match_ireg(cond) {
                                let tmp_cond = self.emit_ireg(cond, f_content, f_context, vm);

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                                // emit: mov tmp_false -> tmp_res
                                self.backend.emit_mov_r_r(&tmp_res, &tmp_false);

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                                // emit: cmp cond_reg 1
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                                self.backend.emit_cmp_imm_r(1, &tmp_cond);
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                                // emit: cmove tmp_true -> tmp_res
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                                self.backend.emit_cmove_r_r(&tmp_res, &tmp_true);
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                            } else {
                                unimplemented!()
                            }
                        } else {
                            // moving vectors, floatingpoints
                            unimplemented!()
                        }
                    },

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                    Instruction_::CmpOp(op, op1, op2) => {
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                        trace!("instsel on CMPOP");
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                        let ops = inst.ops.read().unwrap();
                        let ref op1 = ops[op1];
                        let ref op2 = ops[op2];

                        if self.match_ireg(op1) {
                            debug_assert!(self.match_ireg(op2));

                            let tmp_res = self.get_result_value(node);

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                            // make res64, and set to zero
                            let tmp_res64 = self.make_temporary(f_context, UINT64_TYPE.clone(), vm);
                            self.backend.emit_xor_r_r(&tmp_res64, &tmp_res64);
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                            // set tmp1 as 1 (cmov doesnt allow immediate or reg8 as operand)
                            let tmp_1 = self.make_temporary(f_context, UINT64_TYPE.clone(), vm);
                            self.backend.emit_mov_r_imm(&tmp_1, 1);
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                            // cmov 1 to result
                            match self.emit_cmp_res(node, f_content, f_context, vm) {
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                                op::CmpOp::EQ  => self.backend.emit_cmove_r_r (&tmp_res64, &tmp_1),
                                op::CmpOp::NE  => self.backend.emit_cmovne_r_r(&tmp_res64, &tmp_1),
                                op::CmpOp::SGE => self.backend.emit_cmovge_r_r(&tmp_res64, &tmp_1),
                                op::CmpOp::SGT => self.backend.emit_cmovg_r_r (&tmp_res64, &tmp_1),
                                op::CmpOp::SLE => self.backend.emit_cmovle_r_r(&tmp_res64, &tmp_1),
                                op::CmpOp::SLT => self.backend.emit_cmovl_r_r (&tmp_res64, &tmp_1),
                                op::CmpOp::UGE => self.backend.emit_cmovae_r_r(&tmp_res64, &tmp_1),
                                op::CmpOp::UGT => self.backend.emit_cmova_r_r (&tmp_res64, &tmp_1),
                                op::CmpOp::ULE => self.backend.emit_cmovbe_r_r(&tmp_res64, &tmp_1),
                                op::CmpOp::ULT => self.backend.emit_cmovb_r_r (&tmp_res64, &tmp_1),
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                                _ => panic!("expecting integer comparison op with int values")
                            }
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                            // truncate tmp_res64 to tmp_res (probably u8)
                            self.backend.emit_mov_r_r(&tmp_res, &tmp_res64);
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                        } else {
                            unimplemented!()
                        }
                    }

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                    Instruction_::Branch1(ref dest) => {
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                        trace!("instsel on BRANCH1");
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                        let ops = inst.ops.read().unwrap();
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                        self.process_dest(&ops, dest, f_content, f_context, vm);
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                        let target = f_content.get_block(dest.target).name().unwrap();
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                        trace!("emit branch1");
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                        // jmp
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                        self.backend.emit_jmp(target);
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                    },
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                    Instruction_::Switch{cond, ref default, ref branches} => {
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                        trace!("instsel on SWITCH");
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                        let ops = inst.ops.read().unwrap();

                        let ref cond = ops[cond];

                        if self.match_ireg(cond) {
                            let tmp_cond = self.emit_ireg(cond, f_content, f_context, vm);

                            // emit each branch
                            for &(case_op_index, ref case_dest) in branches {
                                let ref case_op = ops[case_op_index];

                                // process dest
                                self.process_dest(&ops, case_dest, f_content, f_context, vm);

                                let target = f_content.get_block(case_dest.target).name().unwrap();

                                if self.match_iimm(case_op) {
                                    let imm = self.node_iimm_to_i32(case_op);

                                    // cmp case cond
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                                    self.backend.emit_cmp_imm_r(imm, &tmp_cond);
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                                    // je dest
                                    self.backend.emit_je(target);
                                } else if self.match_ireg(case_op) {
                                    let tmp_case_op = self.emit_ireg(case_op, f_content, f_context, vm);

                                    // cmp case cond
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                                    self.backend.emit_cmp_r_r(&tmp_case_op, &tmp_cond);
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                                    // je dest
                                    self.backend.emit_je(target);
                                } else {
                                    panic!("expecting ireg cond to be either iimm or ireg: {}", cond);
                                }
                            }

                            // emit default
                            self.process_dest(&ops, default, f_content, f_context, vm);
                            
                            let default_target = f_content.get_block(default.target).name().unwrap();
                            self.backend.emit_jmp(default_target);
                        } else {
                            panic!("expecting cond in switch to be ireg: {}", cond);
                        }
                    }
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                    Instruction_::ExprCall{ref data, is_abort} => {
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                        trace!("instsel on EXPRCALL");

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                        if is_abort {
                            unimplemented!()
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                        }
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                        self.emit_mu_call(
                            inst, // inst: &Instruction,
                            data, // calldata: &CallData,
                            None, // resumption: Option<&ResumptionData>,
                            node, // cur_node: &TreeNode, 
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                            f_content, f_context, vm);
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                    },
                    
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                    Instruction_::Call{ref data, ref resume} => {
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                        trace!("instsel on CALL");

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                        self.emit_mu_call(
                            inst, 
                            data, 
                            Some(resume), 
                            node, 
                            f_content, f_context, vm);
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                    },

                    Instruction_::ExprCCall{ref data, is_abort} => {
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                        trace!("instsel on EXPRCCALL");

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                        if is_abort {
                            unimplemented!()
                        }

                        self.emit_c_call_ir(inst, data, None, node, f_content, f_context, vm);
                    }

                    Instruction_::CCall{ref data, ref resume} => {
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                        trace!("instsel on CCALL");

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                        self.emit_c_call_ir(inst, data, Some(resume), node, f_content, f_context, vm);
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                    }
                    
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                    Instruction_::Return(_) => {
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                        trace!("instsel on RETURN");

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                        self.emit_common_epilogue(inst, f_content, f_context, vm);
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                        self.backend.emit_ret();
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                    },
                    
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                    Instruction_::BinOp(op, op1, op2) => {
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                        trace!("instsel on BINOP");

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                        let ops = inst.ops.read().unwrap();
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                        let res_tmp = self.get_result_value(node);
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                        match op {
                            op::BinOp::Add => {
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                                if self.match_ireg(&ops[op1]) && self.match_iimm(&ops[op2]) {
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                                    trace!("emit add-ireg-imm");
                                    
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                                    let reg_op1 = self.emit_ireg(&ops[op1], f_content, f_context, vm);
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                                    let reg_op2 = self.node_iimm_to_i32(&ops[op2]);
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                                    // mov op1, res
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                                    self.backend.emit_mov_r_r(&res_tmp, &reg_op1);
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                                    // add op2, res
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                                    self.backend.emit_add_r_imm(&res_tmp, reg_op2);
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                                } else if self.match_ireg(&ops[op1]) && self.match_mem(&ops[op2]) {
                                    trace!("emit add-ireg-mem");
                                    
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                                    let reg_op1 = self.emit_ireg(&ops[op1], f_content, f_context, vm);
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                                    let reg_op2 = self.emit_mem(&ops[op2], vm);
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                                    // mov op1, res
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                                    self.backend.emit_mov_r_r(&res_tmp, &reg_op1);
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                                    // add op2 res
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                                    self.backend.emit_add_r_mem(&res_tmp, &reg_op2);
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                                } else if self.match_ireg(&ops[op1]) && self.match_ireg(&ops[op2]) {
                                    trace!("emit add-ireg-ireg");

                                    let reg_op1 = self.emit_ireg(&ops[op1], f_content, f_context, vm);
                                    let reg_op2 = self.emit_ireg(&ops[op2], f_content, f_context, vm);

                                    // mov op1, res
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                                    self.backend.emit_mov_r_r(&res_tmp, &reg_op1);
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                                    // add op2 res
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                                    self.backend.emit_add_r_r(&res_tmp, &reg_op2);
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                                } else {
                                    unimplemented!()
                                }
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                            },
                            op::BinOp::Sub => {
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                                if self.match_ireg(&ops[op1]) && self.match_iimm(&ops[op2]) {
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                                    trace!("emit sub-ireg-imm");

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                                    let reg_op1 = self.emit_ireg(&ops[op1], f_content, f_context, vm);
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                                    let imm_op2 = self.node_iimm_to_i32(&ops[op2]);
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                                    // mov op1, res
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                                    self.backend.emit_mov_r_r(&res_tmp, &reg_op1);
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                                    // add op2, res
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                                    self.backend.emit_sub_r_imm(&res_tmp, imm_op2);
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                                } else if self.match_ireg(&ops[op1]) && self.match_mem(&ops[op2]) {
                                    trace!("emit sub-ireg-mem");
                                    
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                                    let reg_op1 = self.emit_ireg(&ops[op1], f_content, f_context, vm);
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                                    let mem_op2 = self.emit_mem(&ops[op2], vm);
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                                    // mov op1, res
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                                    self.backend.emit_mov_r_r(&res_tmp, &reg_op1);
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                                    // sub op2 res
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                                    self.backend.emit_sub_r_mem(&res_tmp, &mem_op2);
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                                } else if self.match_ireg(&ops[op1]) && self.match_ireg(&ops[op2]) {
                                    trace!("emit sub-ireg-ireg");
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                                    let reg_op1 = self.emit_ireg(&ops[op1], f_content, f_context, vm);
                                    let reg_op2 = self.emit_ireg(&ops[op2], f_content, f_context, vm);
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                                    // mov op1, res
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                                    self.backend.emit_mov_r_r(&res_tmp, &reg_op1);
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                                    // add op2 res
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                                    self.backend.emit_sub_r_r(&res_tmp, &reg_op2);
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                                } else {
                                    unimplemented!()
                                }
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                            },
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                            op::BinOp::And => {
                                let op1 = &ops[op1];
                                let op2 = &ops[op2];

                                if self.match_ireg(op1) && self.match_iimm(op2) {
                                    trace!("emit and-ireg-iimm");

                                    let tmp_op1 = self.emit_ireg(op1, f_content, f_context, vm);
                                    let imm_op2 = self.node_iimm_to_i32(op2);

                                    // mov op1 -> res
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                                    self.backend.emit_mov_r_r(&res_tmp, &tmp_op1);
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                                    // and op2, res -> res
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                                    self.backend.emit_and_r_imm(&res_tmp, imm_op2);
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                                } else if self.match_ireg(op1) && self.match_mem(op2) {
                                    trace!("emit and-ireg-mem");

                                    let tmp_op1 = self.emit_ireg(op1, f_content, f_context, vm);
                                    let mem_op2 = self.emit_mem(op2, vm);

                                    // mov op1, res
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                                    self.backend.emit_mov_r_r(&res_tmp, &tmp_op1);
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                                    // and op2, res -> res
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                                    self.backend.emit_and_r_mem(&res_tmp, &mem_op2);
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                                } else if self.match_ireg(op1) && self.match_ireg(op2) {
                                    trace!("emit and-ireg-ireg");

                                    let tmp_op1 = self.emit_ireg(op1, f_content, f_context, vm);
                                    let tmp_op2 = self.emit_ireg(op2, f_content, f_context, vm);

                                    // mov op1, res
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                                    self.backend.emit_mov_r_r(&res_tmp, &tmp_op1);
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                                    // and op2, res -> res
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                                    self.backend.emit_and_r_r(&res_tmp, &tmp_op2);
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                                } else {
                                    unimplemented!()
                                }
                            },
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                            op::BinOp::Or => {
                                let op1 = &ops[op1];
                                let op2 = &ops[op2];

                                if self.match_ireg(op1) && self.match_iimm(op2) {
                                    trace!("emit or-ireg-iimm");

                                    let tmp_op1 = self.emit_ireg(op1, f_content, f_context, vm);
                                    let imm_op2 = self.node_iimm_to_i32(op2);

                                    // mov op1 -> res
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                                    self.backend.emit_mov_r_r(&res_tmp, &tmp_op1);
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                                    // Or op2, res -> res
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                                    self.backend.emit_or_r_imm(&res_tmp, imm_op2);
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                                } else if self.match_ireg(op1) && self.match_mem(op2) {
                                    trace!("emit or-ireg-mem");

                                    let tmp_op1 = self.emit_ireg(op1, f_content, f_context, vm);
                                    let mem_op2 = self.emit_mem(op2, vm);

                                    // mov op1, res
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                                    self.backend.emit_mov_r_r(&res_tmp, &tmp_op1);
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                                    // Or op2, res -> res
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                                    self.backend.emit_or_r_mem(&res_tmp, &mem_op2);
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                                } else if self.match_ireg(op1) && self.match_ireg(op2) {
                                    trace!("emit or-ireg-ireg");

                                    let tmp_op1 = self.emit_ireg(op1, f_content, f_context, vm);
                                    let tmp_op2 = self.emit_ireg(op2, f_content, f_context, vm);

                                    // mov op1, res
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                                    self.backend.emit_mov_r_r(&res_tmp, &tmp_op1);
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                                    // Or op2, res -> res
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                                    self.backend.emit_or_r_r(&res_tmp, &tmp_op2);
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                                } else {
                                    unimplemented!()
                                }
                            },
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                            op::BinOp::Xor => {
                                let op1 = &ops[op1];
                                let op2 = &ops[op2];

                                if self.match_ireg(op1) && self.match_iimm(op2) {
                                    trace!("emit xor-ireg-iimm");

                                    let tmp_op1 = self.emit_ireg(op1, f_content, f_context, vm);
                                    let imm_op2 = self.node_iimm_to_i32(op2);

                                    // mov op1 -> res
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                                    self.backend.emit_mov_r_r(&res_tmp, &tmp_op1);
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                                    // xor op2, res -> res
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                                    self.backend.emit_xor_r_imm(&res_tmp, imm_op2);
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                                } else if self.match_ireg(op1) && self.match_mem(op2) {
                                    trace!("emit xor-ireg-mem");

                                    let tmp_op1 = self.emit_ireg(op1, f_content, f_context, vm);
                                    let mem_op2 = self.emit_mem(op2, vm);

                                    // mov op1, res
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                                    self.backend.emit_mov_r_r(&res_tmp, &tmp_op1);
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                                    // xor op2, res -> res
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                                    self.backend.emit_xor_r_mem(&res_tmp, &mem_op2);
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                                } else if self.match_ireg(op1) && self.match_ireg(op2) {
                                    trace!("emit xor-ireg-ireg");

                                    let tmp_op1 = self.emit_ireg(op1, f_content, f_context, vm);
                                    let tmp_op2 = self.emit_ireg(op2, f_content, f_context, vm);

                                    // mov op1, res
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                                    self.backend.emit_mov_r_r(&res_tmp, &tmp_op1);
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                                    // xor op2, res -> res
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                                    self.backend.emit_xor_r_r(&res_tmp, &tmp_op2);
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                                } else {
                                    unimplemented!()
                                }
                            }
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                            op::BinOp::Mul => {
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                                // mov op1 -> rax
                                let op1 = &ops[op1];
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                                let mreg_op1 = match op1.clone_value().ty.get_int_length() {
                                    Some(64) => x86_64::RAX.clone(),
                                    Some(32) => x86_64::EAX.clone(),
                                    Some(16) => x86_64::AX.clone(),
                                    Some(8)  => x86_64::AL.clone(),
                                    _ => unimplemented!()
                                };

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                                if self.match_iimm(op1) {
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                                    let imm_op1 = self.node_iimm_to_i32(op1);
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                                    self.backend.emit_mov_r_imm(&mreg_op1, imm_op1);
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                                } else if self.match_mem(op1) {
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                                    let mem_op1 = self.emit_mem(op1, vm);
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                                    self.backend.emit_mov_r_mem(&mreg_op1, &mem_op1);
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                                } else if self.match_ireg(op1) {
                                    let reg_op1 = self.emit_ireg(op1, f_content, f_context, vm);

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                                    self.backend.emit_mov_r_r(&mreg_op1, &reg_op1);
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                                } else {
                                    unimplemented!();
                                }
                                
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                                // mul op2
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                                let op2 = &ops[op2];
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                                if self.match_iimm(op2) {
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                                    let imm_op2 = self.node_iimm_to_i32(op2);
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                                    // put imm in a temporary
                                    // here we use result reg as temporary
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                                    self.backend.emit_mov_r_imm(&res_tmp, imm_op2);
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                                    self.backend.emit_mul_r(&res_tmp);
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                                } else if self.match_mem(op2) {
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                                    let mem_op2 = self.emit_mem(op2, vm);
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                                    self.backend.emit_mul_mem(&mem_op2);
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                                } else if self.match_ireg(op2) {
                                    let reg_op2 = self.emit_ireg(op2, f_content, f_context, vm);

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                                    self.backend.emit_mul_r(&reg_op2);
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                                } else {
                                    unimplemented!();
                                }
                                
                                // mov rax -> result
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                                match res_tmp.ty.get_int_length() {
                                    Some(64) => self.backend.emit_mov_r_r(&res_tmp, &x86_64::RAX),
                                    Some(32) => self.backend.emit_mov_r_r(&res_tmp, &x86_64::EAX),
                                    Some(16) => self.backend.emit_mov_r_r(&res_tmp, &x86_64::AX),
                                    Some(8)  => self.backend.emit_mov_r_r(&res_tmp, &x86_64::AL),
                                    _ => unimplemented!()
                                }

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                            },
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                            op::BinOp::Udiv => {
                                let op1 = &ops[op1];
                                let op2 = &ops[op2];

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                                self.emit_udiv(op1, op2, f_content, f_context, vm);
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                                // mov rax -> result
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                                match res_tmp.ty.get_int_length() {
                                    Some(64) => {
                                        self.backend.emit_mov_r_r(&res_tmp, &x86_64::RAX);
                                    }
                                    Some(32) => {
                                        self.backend.emit_mov_r_r(&res_tmp, &x86_64::EAX);
                                    }
                                    Some(16) => {
                                        self.backend.emit_mov_r_r(&res_tmp, &x86_64::AX);
                                    }
                                    Some(8)  => {
                                        self.backend.emit_mov_r_r(&res_tmp, &x86_64::AL);
                                    }
                                    _ => unimplemented!()
                                }
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                            },
                            op::BinOp::Sdiv => {
                                let op1 = &ops[op1];
                                let op2 = &ops[op2];
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                                self.emit_idiv(op1, op2, f_content, f_context, vm);
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                                // mov rax -> result
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                                match res_tmp.ty.get_int_length() {
                                    Some(64) => {
                                        self.backend.emit_mov_r_r(&res_tmp, &x86_64::RAX);
                                    }
                                    Some(32) => {
                                        self.backend.emit_mov_r_r(&res_tmp, &x86_64::EAX);
                                    }
                                    Some(16) => {
                                        self.backend.emit_mov_r_r(&res_tmp, &x86_64::AX);
                                    }
                                    Some(8)  => {
                                        self.backend.emit_mov_r_r(&res_tmp, &x86_64::AL);
                                    }
                                    _ => unimplemented!()
                                }
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                            },
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                            op::BinOp::Urem => {
                                let op1 = &ops[op1];
                                let op2 = &ops[op2];

                                self.emit_udiv(op1, op2, f_content, f_context, vm);

                                // mov rdx -> result
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                                match res_tmp.ty.get_int_length() {
                                    Some(64) => {
                                        self.backend.emit_mov_r_r(&res_tmp, &x86_64::RDX);
                                    }
                                    Some(32) => {
                                        self.backend.emit_mov_r_r(&res_tmp, &x86_64::EDX);
                                    }
                                    Some(16) => {
                                        self.backend.emit_mov_r_r(&res_tmp, &x86_64::DX);
                                    }
                                    Some(8)  => {
                                        self.backend.emit_mov_r_r(&res_tmp, &x86_64::AH);
                                    }
                                    _ => unimplemented!()
                                }
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                            },
                            op::BinOp::Srem => {
                                let op1 = &ops[op1];
                                let op2 = &ops[op2];

                                self.emit_idiv(op1, op2, f_content, f_context, vm);

                                // mov rdx -> result
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                                match res_tmp.ty.get_int_length() {
                                    Some(64) => {
                                        self.backend.emit_mov_r_r(&res_tmp, &x86_64::RDX);
                                    }
                                    Some(32) => {
                                        self.backend.emit_mov_r_r(&res_tmp, &x86_64::EDX);
                                    }
                                    Some(16) => {
                                        self.backend.emit_mov_r_r(&res_tmp, &x86_64::DX);
                                    }
                                    Some(8)  => {
                                        self.backend.emit_mov_r_r(&res_tmp, &x86_64::AH);
                                    }
                                    _ => unimplemented!()
                                }
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                            },
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                            op::BinOp::Shl => {
                                let op1 = &ops[op1];
                                let op2 = &ops[op2];

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                                if self.match_mem(op1) {
                                    unimplemented!()
                                } else if self.match_ireg(op1) {
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                                    let tmp_op1 = self.emit_ireg(op1, f_content, f_context, vm);

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                                    if self.match_iimm(op2) {
                                        let imm_op2 = self.node_iimm_to_i32(op2) as i8;

                                        // shl op1, op2 -> op1
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                                        self.backend.emit_shl_r_imm8(&tmp_op1, imm_op2);
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                                        // mov op1 -> result
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                                        self.backend.emit_mov_r_r(&res_tmp, &tmp_op1);
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                                    } else if self.match_ireg(op2) {
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                                        let tmp_op2 = self.emit_ireg(op2, f_content, f_context, vm);

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                                        // mov op2 -> cl
                                        self.backend.emit_mov_r_r(&x86_64::CL, &tmp_op2);
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                                        // shl op1, cl -> op1
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                                        self.backend.emit_shl_r_cl(&tmp_op1);
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                                        // mov op1 -> result
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                                        self.backend.emit_mov_r_r(&res_tmp, &tmp_op1);
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                                    } else {
                                        panic!("unexpected op2 (not ireg not iimm): {}", op2);
                                    }
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                                } else {
                                    panic!("unexpected op1 (not ireg not mem): {}", op1);
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                                }
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                            },
                            op::BinOp::Lshr => {
                                let op1 = &ops[op1];
                                let op2 = &ops[op2];

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                                if self.match_mem(op1) {
                                    unimplemented!()
                                } else if self.match_ireg(op1) {
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                                    let tmp_op1 = self.emit_ireg(op1, f_content, f_context, vm);

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                                    if self.match_iimm(op2) {
                                        let imm_op2 = self.node_iimm_to_i32(op2) as i8;

                                        // shr op1, op2 -> op1
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                                        self.backend.emit_shr_r_imm8(&tmp_op1, imm_op2);
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                                        // mov op1 -> result
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                                        self.backend.emit_mov_r_r(&res_tmp, &tmp_op1);
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                                    } else if self.match_ireg(op2) {
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                                        let tmp_op2 = self.emit_ireg(op2, f_content, f_context, vm);

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                                        // mov op2 -> cl
                                        self.backend.emit_mov_r_r(&x86_64::CL, &tmp_op2);
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                                        // shr op1, cl -> op1
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                                        self.backend.emit_shr_r_cl(&tmp_op1);
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                                        // mov op1 -> result
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                                        self.backend.emit_mov_r_r(&res_tmp, &tmp_op1);
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                                    } else {
                                        panic!("unexpected op2 (not ireg not iimm): {}", op2);
                                    }
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                                } else {
                                    panic!("unexpected op1 (not ireg not mem): {}", op1);
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                                }
                            },
                            op::BinOp::Ashr => {
                                let op1 = &ops[op1];
                                let op2 = &ops[op2];

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                                if self.match_mem(op1) {
                                    unimplemented!()
                                } else if self.match_ireg(op1) {
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                                    let tmp_op1 = self.emit_ireg(op1, f_content, f_context, vm);

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                                    if self.match_iimm(op2) {
                                        let imm_op2 = self.node_iimm_to_i32(op2) as i8;

                                        // sar op1, op2 -> op1
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                                        self.backend.emit_sar_r_imm8(&tmp_op1, imm_op2);
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                                        // mov op1 -> result
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                                        self.backend.emit_mov_r_r(&res_tmp, &tmp_op1);
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                                    } else if self.match_ireg(op2) {
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                                        let tmp_op2 = self.emit_ireg(op2, f_content, f_context, vm);

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                                        // mov op2 -> cl
                                        self.backend.emit_mov_r_r(&x86_64::CL, &tmp_op2);
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                                        // sar op1, cl -> op1
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                                        self.backend.emit_sar_r_cl(&tmp_op1);
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                                        // mov op1 -> result
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                                        self.backend.emit_mov_r_r(&res_tmp, &tmp_op1);
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                                    } else  {
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                                        panic!("unexpected op2 (not ireg not iimm): {}", op2);
                                    }
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                                } else {
                                    panic!("unexpected op1 (not ireg not mem): {}", op1);
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                                }
                            },

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                            // floating point
                            op::BinOp::FAdd => {
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                                if self.match_fpreg(&ops[op1]) && self.match_mem(&ops[op2]) {
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                                    trace!("emit add-fpreg-mem");

                                    let reg_op1 = self.emit_fpreg(&ops[op1], f_content, f_context, vm);
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                                    let mem_op2 = self.emit_mem(&ops[op2], vm);
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                                    // mov op1, res
                                    self.backend.emit_movsd_f64_f64(&res_tmp, &reg_op1);
                                    // sub op2 res
                                    self.backend.emit_addsd_f64_mem64(&res_tmp, &mem_op2);
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                                } else if self.match_fpreg(&ops[op1]) && self.match_fpreg(&ops[op2]) {
                                    trace!("emit add-fpreg-fpreg");

                                    let reg_op1 = self.emit_fpreg(&ops[op1], f_content, f_context, vm);
                                    let reg_op2 = self.emit_fpreg(&ops[op2], f_content, f_context, vm);

                                    // movsd op1, res
                                    self.backend.emit_movsd_f64_f64(&res_tmp, &reg_op1);
                                    // add op2 res
                                    self.backend.emit_addsd_f64_f64(&res_tmp, &reg_op2);
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                                } else {
                                    unimplemented!()
                                }
                            }
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                            _ => unimplemented!()
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                        }
                    }
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                    Instruction_::ConvOp{operation, ref from_ty, ref to_ty, operand} => {
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                        trace!("instsel on CONVOP");

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                        let ops = inst.ops.read().unwrap();

                        let ref op = ops[operand];

                        match operation {
                            op::ConvOp::TRUNC => {
                                if self.match_ireg(op) {
                                    let tmp_op = self.emit_ireg(op, f_content, f_context, vm);
                                    let tmp_res = self.get_result_value(node);

                                    // mov op -> result
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                                    self.backend.emit_mov_r_r(&tmp_res, &tmp_op);
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                                } else {
                                    panic!("unexpected op (expect ireg): {}", op);
                                }
                            }
                            op::ConvOp::ZEXT => {
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                                if self.match_ireg(op) {
                                    let tmp_op = self.emit_ireg(op, f_content, f_context, vm);
                                    let tmp_res = self.get_result_value(node);
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                                    // movz op -> result
                                    let from_ty_size = vm.get_backend_type_info(from_ty.id()).size;
                                    let to_ty_size   = vm.get_backend_type_info(to_ty.id()).size;
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                                    if from_ty_size != to_ty_size {
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                                        if from_ty_size == 4 && to_ty_size == 8 {
                                            // zero extend from 32 bits to 64 bits is a mov instruction
                                            // x86 does not have movzlq (32 to 64)

                                            // tmp_op is int32, but tmp_res is int64
                                            // we want to force a 32-to-32 mov, so high bits of the destination will be zeroed

                                            let tmp_res32 = unsafe {tmp_res.as_type(UINT32_TYPE.clone())};

                                            self.backend.emit_mov_r_r(&tmp_res32, &tmp_op);
                                        } else {
                                            self.backend.emit_movz_r_r(&tmp_res, &tmp_op);
                                        }
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                                    } else {
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                                        self.backend.emit_mov_r_r(&tmp_res, &tmp_op);
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                                    }
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                                } else {
                                    panic!("unexpected op (expect ireg): {}", op);
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                                }
                            },
                            op::ConvOp::SEXT => {
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                                if self.match_ireg(op) {
                                    let tmp_op = self.emit_ireg(op, f_content, f_context, vm);
                                    let tmp_res = self.get_result_value(node);
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                                    // movs op -> result
                                    let from_ty_size = vm.get_backend_type_info(from_ty.id()).size;
                                    let to_ty_size   = vm.get_backend_type_info(to_ty.id()).size;
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                                    if from_ty_size != to_ty_size {
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                                        self.backend.emit_movs_r_r(&tmp_res, &tmp_op);
                                    } else {
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                                        self.backend.emit_mov_r_r(&tmp_res, &tmp_op);
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                                    }
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                                } else {
                                    panic!("unexpected op (expect ireg): {}", op)
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                                }
                            }
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                            op::ConvOp::REFCAST | op::ConvOp::PTRCAST => {
                                // just a mov (and hopefully reg alloc will coalesce it)
                                let tmp_res = self.get_result_value(node);

                                if self.match_ireg(op) {
                                    let tmp_op = self.emit_ireg(op, f_content, f_context, vm);
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                                    self.backend.emit_mov_r_r(&tmp_res, &tmp_op);
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                                } else {
                                    panic!("unexpected op (expect ireg): {}", op)
                                }
                            }
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                            _ => unimplemented!()
                        }
                    }
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                    // load on x64 generates mov inst (no matter what order is specified)
                    // https://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
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                    Instruction_::Load{is_ptr, order, mem_loc} => {
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                        trace!("instsel on LOAD");

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                        let ops = inst.ops.read().unwrap();
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                        let ref loc_op = ops[mem_loc];
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                        // check order
                        match order {
                            MemoryOrder::Relaxed 
                            | MemoryOrder::Consume 
                            | MemoryOrder::Acquire
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                            | MemoryOrder::SeqCst
                            | MemoryOrder::NotAtomic => {},
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                            _ => panic!("didnt expect order {:?} with store inst", order)
                        }                        
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                        let resolved_loc = self.emit_node_addr_to_value(loc_op, f_content, f_context, vm);
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                        let res_temp = self.get_result_value(node);
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                        if self.match_ireg(node) {
                            // emit mov(GPR)
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                            self.backend.emit_mov_r_mem(&res_temp, &resolved_loc);
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                        } else {
                            // emit mov(FPR)
                            unimplemented!()
                        }
                    }
                    
                    Instruction_::Store{is_ptr, order, mem_loc, value} => {
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                        trace!("instsel on STORE");