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inst_sel.rs 91.4 KB
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use ast::ir::*;
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use ast::ptr::*;
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use ast::inst::*;
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use ast::op;
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use ast::op::OpCode;
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use ast::types;
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use ast::types::*;
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use vm::VM;
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use runtime::mm;
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use runtime::ValueLocation;
use runtime::thread;
use runtime::entrypoints;
use runtime::entrypoints::RuntimeEntrypoint;
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use compiler::CompilerPass;
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use compiler::backend;
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use compiler::backend::PROLOGUE_BLOCK_NAME;
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use compiler::backend::x86_64;
use compiler::backend::x86_64::CodeGenerator;
use compiler::backend::x86_64::ASMCodeGen;
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use compiler::machine_code::CompiledFunction;
use compiler::frame::Frame;
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use std::collections::HashMap;
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use std::any::Any;
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pub struct InstructionSelection {
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    name: &'static str,
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    backend: Box<CodeGenerator>,
    
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    current_callsite_id: usize,
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    current_frame: Option<Frame>,
    current_block: Option<MuName>,
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    current_func_start: Option<ValueLocation>,
    // key: block id, val: callsite that names the block as exception block
    current_exn_callsites: HashMap<MuID, Vec<ValueLocation>>,
    // key: block id, val: block location
    current_exn_blocks: HashMap<MuID, ValueLocation>     
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}

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impl <'a> InstructionSelection {
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    #[cfg(feature = "aot")]
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    pub fn new() -> InstructionSelection {
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        InstructionSelection{
            name: "Instruction Selection (x64)",
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            backend: Box::new(ASMCodeGen::new()),
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            current_callsite_id: 0,
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            current_frame: None,
            current_block: None,
            current_func_start: None,
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            // key: block id, val: callsite that names the block as exception block
            current_exn_callsites: HashMap::new(), 
            current_exn_blocks: HashMap::new()
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        }
    }
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    #[cfg(feature = "jit")]
    pub fn new() -> InstructionSelection {
        unimplemented!()
    }
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    // in this pass, we assume that
    // 1. all temporaries will use 64bit registers
    // 2. we do not need to backup/restore caller-saved registers
    // 3. we need to backup/restore all the callee-saved registers
    // if any of these assumption breaks, we will need to re-emit the code
    #[allow(unused_variables)]
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    fn instruction_select(&mut self, node: &'a TreeNode, f_content: &FunctionContent, f_context: &mut FunctionContext, vm: &VM) {
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        trace!("instsel on node {}", node);
        
        match node.v {
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            TreeNode_::Instruction(ref inst) => {
                match inst.v {
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                    Instruction_::Branch2{cond, ref true_dest, ref false_dest, true_prob} => {
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                        // 'branch_if_true' == true, we emit cjmp the same as CmpOp  (je  for EQ, jne for NE)
                        // 'branch_if_true' == false, we emit opposite cjmp as CmpOp (jne for EQ, je  for NE)
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                        let (fallthrough_dest, branch_dest, branch_if_true) = {
                            if true_prob > 0.5f32 {
                                (true_dest, false_dest, false)
                            } else {
                                (false_dest, true_dest, true)
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                            }
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                        };
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                        let ops = inst.ops.read().unwrap();
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                        self.process_dest(&ops, fallthrough_dest, f_content, f_context, vm);
                        self.process_dest(&ops, branch_dest, f_content, f_context, vm);
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                        let branch_target = f_content.get_block(branch_dest.target).name().unwrap();
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                        let ref cond = ops[cond];
                        
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                        if self.match_cmp_res(cond) {
                            trace!("emit cmp_eq-branch2");
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                            match self.emit_cmp_res(cond, f_content, f_context, vm) {
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                                op::CmpOp::EQ => {
                                    if branch_if_true {
                                        self.backend.emit_je(branch_target);
                                    } else {
                                        self.backend.emit_jne(branch_target);
                                    }
                                },
                                op::CmpOp::NE => {
                                    if branch_if_true {
                                        self.backend.emit_jne(branch_target);
                                    } else {
                                        self.backend.emit_je(branch_target);
                                    }
                                },
                                op::CmpOp::UGE => {
                                    if branch_if_true {
                                        self.backend.emit_jae(branch_target);
                                    } else {
                                        self.backend.emit_jb(branch_target);
                                    }
                                },
                                op::CmpOp::UGT => {
                                    if branch_if_true {
                                        self.backend.emit_ja(branch_target);
                                    } else {
                                        self.backend.emit_jbe(branch_target);
                                    }
                                },
                                op::CmpOp::ULE => {
                                    if branch_if_true {
                                        self.backend.emit_jbe(branch_target);
                                    } else {
                                        self.backend.emit_ja(branch_target);
                                    }
                                },
                                op::CmpOp::ULT => {
                                    if branch_if_true {
                                        self.backend.emit_jb(branch_target);
                                    } else {
                                        self.backend.emit_jae(branch_target);
                                    }
                                },
                                op::CmpOp::SGE => {
                                    if branch_if_true {
                                        self.backend.emit_jge(branch_target);
                                    } else {
                                        self.backend.emit_jl(branch_target);
                                    }
                                },
                                op::CmpOp::SGT => {
                                    if branch_if_true {
                                        self.backend.emit_jg(branch_target);
                                    } else {
                                        self.backend.emit_jle(branch_target);
                                    }
                                },
                                op::CmpOp::SLE => {
                                    if branch_if_true {
                                        self.backend.emit_jle(branch_target);
                                    } else {
                                        self.backend.emit_jg(branch_target);
                                    }
                                },
                                op::CmpOp::SLT => {
                                    if branch_if_true {
                                        self.backend.emit_jl(branch_target);
                                    } else {
                                        self.backend.emit_jge(branch_target);
                                    }
                                },
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                                _ => unimplemented!()
                            }
                        } else if self.match_ireg(cond) {
                            trace!("emit ireg-branch2");
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                            let cond_reg = self.emit_ireg(cond, f_content, f_context, vm);
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                            // emit: cmp cond_reg 1
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                            self.backend.emit_cmp_imm32_r64(1, &cond_reg);
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                            // emit: je #branch_dest
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                            self.backend.emit_je(branch_target);
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                        } else {
                            unimplemented!();
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                        }
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                    },
                    
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                    Instruction_::Branch1(ref dest) => {
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                        let ops = inst.ops.read().unwrap();
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                        self.process_dest(&ops, dest, f_content, f_context, vm);
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                        let target = f_content.get_block(dest.target).name().unwrap();
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                        trace!("emit branch1");
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                        // jmp
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                        self.backend.emit_jmp(target);
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                    },
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                    Instruction_::Switch{cond, ref default, ref branches} => {
                        let ops = inst.ops.read().unwrap();

                        let ref cond = ops[cond];

                        if self.match_ireg(cond) {
                            let tmp_cond = self.emit_ireg(cond, f_content, f_context, vm);

                            // emit each branch
                            for &(case_op_index, ref case_dest) in branches {
                                let ref case_op = ops[case_op_index];

                                // process dest
                                self.process_dest(&ops, case_dest, f_content, f_context, vm);

                                let target = f_content.get_block(case_dest.target).name().unwrap();

                                if self.match_iimm(case_op) {
                                    let imm = self.node_iimm_to_i32(case_op);

                                    // cmp case cond
                                    self.backend.emit_cmp_imm32_r64(imm, &tmp_cond);
                                    // je dest
                                    self.backend.emit_je(target);
                                } else if self.match_ireg(case_op) {
                                    let tmp_case_op = self.emit_ireg(case_op, f_content, f_context, vm);

                                    // cmp case cond
                                    self.backend.emit_cmp_r64_r64(&tmp_case_op, &tmp_cond);
                                    // je dest
                                    self.backend.emit_je(target);
                                } else {
                                    panic!("expecting ireg cond to be either iimm or ireg: {}", cond);
                                }
                            }

                            // emit default
                            self.process_dest(&ops, default, f_content, f_context, vm);
                            
                            let default_target = f_content.get_block(default.target).name().unwrap();
                            self.backend.emit_jmp(default_target);
                        } else {
                            panic!("expecting cond in switch to be ireg: {}", cond);
                        }
                    }
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                    Instruction_::ExprCall{ref data, is_abort} => {
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                        if is_abort {
                            unimplemented!()
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                        }
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                        self.emit_mu_call(
                            inst, // inst: &Instruction,
                            data, // calldata: &CallData,
                            None, // resumption: Option<&ResumptionData>,
                            node, // cur_node: &TreeNode, 
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                            f_content, f_context, vm);
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                    },
                    
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                    Instruction_::Call{ref data, ref resume} => {
                        self.emit_mu_call(
                            inst, 
                            data, 
                            Some(resume), 
                            node, 
                            f_content, f_context, vm);
                    }
                    
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                    Instruction_::Return(_) => {
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                        self.emit_common_epilogue(inst, f_content, f_context, vm);
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                        self.backend.emit_ret();
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                    },
                    
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                    Instruction_::BinOp(op, op1, op2) => {
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                        let ops = inst.ops.read().unwrap();
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                        let res_tmp = self.get_result_value(node);
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                        match op {
                            op::BinOp::Add => {
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                                if self.match_ireg(&ops[op1]) && self.match_iimm(&ops[op2]) {
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                                    trace!("emit add-ireg-imm");
                                    
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                                    let reg_op1 = self.emit_ireg(&ops[op1], f_content, f_context, vm);
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                                    let reg_op2 = self.node_iimm_to_i32(&ops[op2]);
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                                    // mov op1, res
                                    self.backend.emit_mov_r64_r64(&res_tmp, &reg_op1);
                                    // add op2, res
                                    self.backend.emit_add_r64_imm32(&res_tmp, reg_op2);
                                } else if self.match_ireg(&ops[op1]) && self.match_mem(&ops[op2]) {
                                    trace!("emit add-ireg-mem");
                                    
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                                    let reg_op1 = self.emit_ireg(&ops[op1], f_content, f_context, vm);
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                                    let reg_op2 = self.emit_mem(&ops[op2], vm);
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                                    // mov op1, res
                                    self.backend.emit_mov_r64_r64(&res_tmp, &reg_op1);
                                    // add op2 res
                                    self.backend.emit_add_r64_mem64(&res_tmp, &reg_op2);
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                                } else if self.match_ireg(&ops[op1]) && self.match_ireg(&ops[op2]) {
                                    trace!("emit add-ireg-ireg");

                                    let reg_op1 = self.emit_ireg(&ops[op1], f_content, f_context, vm);
                                    let reg_op2 = self.emit_ireg(&ops[op2], f_content, f_context, vm);

                                    // mov op1, res
                                    self.backend.emit_mov_r64_r64(&res_tmp, &reg_op1);
                                    // add op2 res
                                    self.backend.emit_add_r64_r64(&res_tmp, &reg_op2);
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                                } else {
                                    unimplemented!()
                                }
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                            },
                            op::BinOp::Sub => {
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                                if self.match_ireg(&ops[op1]) && self.match_iimm(&ops[op2]) {
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                                    trace!("emit sub-ireg-imm");

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                                    let reg_op1 = self.emit_ireg(&ops[op1], f_content, f_context, vm);
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                                    let imm_op2 = self.node_iimm_to_i32(&ops[op2]);
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                                    // mov op1, res
                                    self.backend.emit_mov_r64_r64(&res_tmp, &reg_op1);
                                    // add op2, res
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                                    self.backend.emit_sub_r64_imm32(&res_tmp, imm_op2);
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                                } else if self.match_ireg(&ops[op1]) && self.match_mem(&ops[op2]) {
                                    trace!("emit sub-ireg-mem");
                                    
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                                    let reg_op1 = self.emit_ireg(&ops[op1], f_content, f_context, vm);
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                                    let mem_op2 = self.emit_mem(&ops[op2], vm);
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                                    // mov op1, res
                                    self.backend.emit_mov_r64_r64(&res_tmp, &reg_op1);
                                    // sub op2 res
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                                    self.backend.emit_sub_r64_mem64(&res_tmp, &mem_op2);
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                                } else if self.match_ireg(&ops[op1]) && self.match_ireg(&ops[op2]) {
                                    trace!("emit sub-ireg-ireg");
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                                    let reg_op1 = self.emit_ireg(&ops[op1], f_content, f_context, vm);
                                    let reg_op2 = self.emit_ireg(&ops[op2], f_content, f_context, vm);
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                                    // mov op1, res
                                    self.backend.emit_mov_r64_r64(&res_tmp, &reg_op1);
                                    // add op2 res
                                    self.backend.emit_sub_r64_r64(&res_tmp, &reg_op2);
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                                } else {
                                    unimplemented!()
                                }
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                            },
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                            op::BinOp::And => {
                                let op1 = &ops[op1];
                                let op2 = &ops[op2];

                                if self.match_ireg(op1) && self.match_iimm(op2) {
                                    trace!("emit and-ireg-iimm");

                                    let tmp_op1 = self.emit_ireg(op1, f_content, f_context, vm);
                                    let imm_op2 = self.node_iimm_to_i32(op2);

                                    // mov op1 -> res
                                    self.backend.emit_mov_r64_r64(&res_tmp, &tmp_op1);
                                    // and op2, res -> res
                                    self.backend.emit_and_r64_imm32(&res_tmp, imm_op2);
                                } else if self.match_ireg(op1) && self.match_mem(op2) {
                                    trace!("emit and-ireg-mem");

                                    let tmp_op1 = self.emit_ireg(op1, f_content, f_context, vm);
                                    let mem_op2 = self.emit_mem(op2, vm);

                                    // mov op1, res
                                    self.backend.emit_mov_r64_r64(&res_tmp, &tmp_op1);
                                    // and op2, res -> res
                                    self.backend.emit_and_r64_mem64(&res_tmp, &mem_op2);
                                } else if self.match_ireg(op1) && self.match_ireg(op2) {
                                    trace!("emit and-ireg-ireg");

                                    let tmp_op1 = self.emit_ireg(op1, f_content, f_context, vm);
                                    let tmp_op2 = self.emit_ireg(op2, f_content, f_context, vm);

                                    // mov op1, res
                                    self.backend.emit_mov_r64_r64(&res_tmp, &tmp_op1);
                                    // and op2, res -> res
                                    self.backend.emit_and_r64_r64(&res_tmp, &tmp_op2);
                                } else {
                                    unimplemented!()
                                }
                            },
                            op::BinOp::Xor => {
                                let op1 = &ops[op1];
                                let op2 = &ops[op2];

                                if self.match_ireg(op1) && self.match_iimm(op2) {
                                    trace!("emit xor-ireg-iimm");

                                    let tmp_op1 = self.emit_ireg(op1, f_content, f_context, vm);
                                    let imm_op2 = self.node_iimm_to_i32(op2);

                                    // mov op1 -> res
                                    self.backend.emit_mov_r64_r64(&res_tmp, &tmp_op1);
                                    // xor op2, res -> res
                                    self.backend.emit_xor_r64_imm32(&res_tmp, imm_op2);
                                } else if self.match_ireg(op1) && self.match_mem(op2) {
                                    trace!("emit xor-ireg-mem");

                                    let tmp_op1 = self.emit_ireg(op1, f_content, f_context, vm);
                                    let mem_op2 = self.emit_mem(op2, vm);

                                    // mov op1, res
                                    self.backend.emit_mov_r64_r64(&res_tmp, &tmp_op1);
                                    // xor op2, res -> res
                                    self.backend.emit_xor_r64_mem64(&res_tmp, &mem_op2);
                                } else if self.match_ireg(op1) && self.match_ireg(op2) {
                                    trace!("emit xor-ireg-ireg");

                                    let tmp_op1 = self.emit_ireg(op1, f_content, f_context, vm);
                                    let tmp_op2 = self.emit_ireg(op2, f_content, f_context, vm);

                                    // mov op1, res
                                    self.backend.emit_mov_r64_r64(&res_tmp, &tmp_op1);
                                    // xor op2, res -> res
                                    self.backend.emit_xor_r64_r64(&res_tmp, &tmp_op2);
                                } else {
                                    unimplemented!()
                                }
                            }
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                            op::BinOp::Mul => {
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                                // mov op1 -> rax
                                let rax = x86_64::RAX.clone();
                                let op1 = &ops[op1];
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                                if self.match_iimm(op1) {
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                                    let imm_op1 = self.node_iimm_to_i32(op1);
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                                    self.backend.emit_mov_r64_imm32(&rax, imm_op1);
                                } else if self.match_mem(op1) {
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                                    let mem_op1 = self.emit_mem(op1, vm);
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                                    self.backend.emit_mov_r64_mem64(&rax, &mem_op1);
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                                } else if self.match_ireg(op1) {
                                    let reg_op1 = self.emit_ireg(op1, f_content, f_context, vm);

                                    self.backend.emit_mov_r64_r64(&rax, &reg_op1);
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                                } else {
                                    unimplemented!();
                                }
                                
                                // mul op2 -> rax
                                let op2 = &ops[op2];
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                                if self.match_iimm(op2) {
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                                    let imm_op2 = self.node_iimm_to_i32(op2);
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                                    // put imm in a temporary
                                    // here we use result reg as temporary
                                    self.backend.emit_mov_r64_imm32(&res_tmp, imm_op2);
                                    
                                    self.backend.emit_mul_r64(&res_tmp);
                                } else if self.match_mem(op2) {
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                                    let mem_op2 = self.emit_mem(op2, vm);
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                                    self.backend.emit_mul_mem64(&mem_op2);
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                                } else if self.match_ireg(op2) {
                                    let reg_op2 = self.emit_ireg(op2, f_content, f_context, vm);

                                    self.backend.emit_mul_r64(&reg_op2);
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                                } else {
                                    unimplemented!();
                                }
                                
                                // mov rax -> result
                                self.backend.emit_mov_r64_r64(&res_tmp, &rax);
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                            },
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                            op::BinOp::Udiv => {
                                let op1 = &ops[op1];
                                let op2 = &ops[op2];

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                                self.emit_udiv(op1, op2, f_content, f_context, vm);
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                                // mov rax -> result
                                self.backend.emit_mov_r64_r64(&res_tmp, &x86_64::RAX);
                            },
                            op::BinOp::Sdiv => {
                                let op1 = &ops[op1];
                                let op2 = &ops[op2];
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                                self.emit_idiv(op1, op2, f_content, f_context, vm);
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                                // mov rax -> result
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                                self.backend.emit_mov_r64_r64(&res_tmp, &x86_64::RAX);
                            },
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                            op::BinOp::Urem => {
                                let op1 = &ops[op1];
                                let op2 = &ops[op2];

                                self.emit_udiv(op1, op2, f_content, f_context, vm);

                                // mov rdx -> result
                                self.backend.emit_mov_r64_r64(&res_tmp, &x86_64::RDX);
                            },
                            op::BinOp::Srem => {
                                let op1 = &ops[op1];
                                let op2 = &ops[op2];

                                self.emit_idiv(op1, op2, f_content, f_context, vm);

                                // mov rdx -> result
                                self.backend.emit_mov_r64_r64(&res_tmp, &x86_64::RDX);
                            },
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                            op::BinOp::Shl => {
                                let op1 = &ops[op1];
                                let op2 = &ops[op2];

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                                if self.match_mem(op1) {
                                    unimplemented!()
                                } else if self.match_ireg(op1) {
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                                    let tmp_op1 = self.emit_ireg(op1, f_content, f_context, vm);

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                                    if self.match_iimm(op2) {
                                        let imm_op2 = self.node_iimm_to_i32(op2) as i8;

                                        // shl op1, op2 -> op1
                                        self.backend.emit_shl_r64_imm8(&tmp_op1, imm_op2);

                                        // mov op1 -> result
                                        self.backend.emit_mov_r64_r64(&res_tmp, &tmp_op1);
                                    } else if self.match_ireg(op2) {
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                                        let tmp_op2 = self.emit_ireg(op2, f_content, f_context, vm);

                                        // mov op2 -> rcx
                                        self.backend.emit_mov_r64_r64(&x86_64::RCX, &tmp_op2);

                                        // shl op1, cl -> op1
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                                        self.backend.emit_shl_r64_cl(&tmp_op1);
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                                        // mov op1 -> result
                                        self.backend.emit_mov_r64_r64(&res_tmp, &tmp_op1);
                                    } else {
                                        panic!("unexpected op2 (not ireg not iimm): {}", op2);
                                    }
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                                } else {
                                    panic!("unexpected op1 (not ireg not mem): {}", op1);
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                                }
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                            },
                            op::BinOp::Lshr => {
                                let op1 = &ops[op1];
                                let op2 = &ops[op2];

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                                if self.match_mem(op1) {
                                    unimplemented!()
                                } else if self.match_ireg(op1) {
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                                    let tmp_op1 = self.emit_ireg(op1, f_content, f_context, vm);

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                                    if self.match_iimm(op2) {
                                        let imm_op2 = self.node_iimm_to_i32(op2) as i8;

                                        // shr op1, op2 -> op1
                                        self.backend.emit_shr_r64_imm8(&tmp_op1, imm_op2);

                                        // mov op1 -> result
                                        self.backend.emit_mov_r64_r64(&res_tmp, &tmp_op1);
                                    } else if self.match_ireg(op2) {
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                                        let tmp_op2 = self.emit_ireg(op2, f_content, f_context, vm);

                                        // mov op2 -> rcx
                                        self.backend.emit_mov_r64_r64(&x86_64::RCX, &tmp_op2);

                                        // shr op1, cl -> op1
                                        self.backend.emit_shr_r64_cl(&tmp_op1);

                                        // mov op1 -> result
                                        self.backend.emit_mov_r64_r64(&res_tmp, &tmp_op1);
                                    } else {
                                        panic!("unexpected op2 (not ireg not iimm): {}", op2);
                                    }
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                                } else {
                                    panic!("unexpected op1 (not ireg not mem): {}", op1);
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                                }
                            },
                            op::BinOp::Ashr => {
                                let op1 = &ops[op1];
                                let op2 = &ops[op2];

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                                if self.match_mem(op1) {
                                    unimplemented!()
                                } else if self.match_ireg(op1) {
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                                    let tmp_op1 = self.emit_ireg(op1, f_content, f_context, vm);

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                                    if self.match_iimm(op2) {
                                        let imm_op2 = self.node_iimm_to_i32(op2) as i8;

                                        // sar op1, op2 -> op1
                                        self.backend.emit_sar_r64_imm8(&tmp_op1, imm_op2);

                                        // mov op1 -> result
                                        self.backend.emit_mov_r64_r64(&res_tmp, &tmp_op1);
                                    } else if self.match_ireg(op2) {
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                                        let tmp_op2 = self.emit_ireg(op2, f_content, f_context, vm);

                                        // mov op2 -> rcx
                                        self.backend.emit_mov_r64_r64(&x86_64::RCX, &tmp_op2);

                                        // sar op1, cl -> op1
                                        self.backend.emit_sar_r64_cl(&tmp_op1);

                                        // mov op1 -> result
                                        self.backend.emit_mov_r64_r64(&res_tmp, &tmp_op1);
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                                    } else  {
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                                        panic!("unexpected op2 (not ireg not iimm): {}", op2);
                                    }
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                                } else {
                                    panic!("unexpected op1 (not ireg not mem): {}", op1);
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                                }
                            },

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                            // floating point
                            op::BinOp::FAdd => {
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                                if self.match_fpreg(&ops[op1]) && self.match_mem(&ops[op2]) {
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                                    trace!("emit add-fpreg-mem");

                                    let reg_op1 = self.emit_fpreg(&ops[op1], f_content, f_context, vm);
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                                    let mem_op2 = self.emit_mem(&ops[op2], vm);
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                                    // mov op1, res
                                    self.backend.emit_movsd_f64_f64(&res_tmp, &reg_op1);
                                    // sub op2 res
                                    self.backend.emit_addsd_f64_mem64(&res_tmp, &mem_op2);
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                                } else if self.match_fpreg(&ops[op1]) && self.match_fpreg(&ops[op2]) {
                                    trace!("emit add-fpreg-fpreg");

                                    let reg_op1 = self.emit_fpreg(&ops[op1], f_content, f_context, vm);
                                    let reg_op2 = self.emit_fpreg(&ops[op2], f_content, f_context, vm);

                                    // movsd op1, res
                                    self.backend.emit_movsd_f64_f64(&res_tmp, &reg_op1);
                                    // add op2 res
                                    self.backend.emit_addsd_f64_f64(&res_tmp, &reg_op2);
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                                } else {
                                    unimplemented!()
                                }
                            }
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                            _ => unimplemented!()
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                        }
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                        // truncate result
                        if res_tmp.is_int_reg() {
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                            self.emit_truncate_result(&UINT64_TYPE, &res_tmp.ty, &res_tmp, f_context, vm);
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                        }
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                    }
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                    Instruction_::ConvOp{operation, ref from_ty, ref to_ty, operand} => {
                        let ops = inst.ops.read().unwrap();

                        let ref op = ops[operand];

                        let extract_int_len = |x: &P<MuType>| {
                            match x.v {
                                MuType_::Int(len) => len,
                                _ => panic!("only expect int types, found: {}", x)
                            }
                        };

                        match operation {
                            op::ConvOp::TRUNC => {
                                // currently only use 64bits register
                                // so only keep what is needed in the register (set others to 0)

                                if self.match_ireg(op) {
                                    let tmp_op = self.emit_ireg(op, f_content, f_context, vm);
                                    let tmp_res = self.get_result_value(node);

                                    // mov op -> result
                                    self.backend.emit_mov_r64_r64(&tmp_res, &tmp_op);

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                                    // truncate result
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                                    self.emit_truncate_result(from_ty, to_ty, &tmp_res, f_context, vm);
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                                } else {
                                    panic!("unexpected op (expect ireg): {}", op);
                                }
                            }
                            op::ConvOp::ZEXT => {
                                // currently only use 64bits register
                                // so set irrelevant bits to 0
                                let from_ty_len = extract_int_len(from_ty);
                                let to_ty_len   = extract_int_len(to_ty);

                                if self.match_ireg(op) {
                                    let tmp_op = self.emit_ireg(op, f_content, f_context, vm);
                                    let tmp_res = self.get_result_value(node);

                                    let mask = match from_ty_len {
                                        8  => 0xFFi32,
                                        16 => 0xFFFFi32,
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                                        32 => 0xFFFFFFFFi32,
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                                        _ => unimplemented!()
                                    };

                                    // mov op -> result
                                    self.backend.emit_mov_r64_r64(&tmp_res, &tmp_op);

                                    // and mask result -> result
                                    self.backend.emit_and_r64_imm32(&tmp_res, mask);
                                } else {
                                    panic!("unexpected op (expect ireg): {}", op);
                                }
                            },
                            op::ConvOp::SEXT => {
                                // currently only use 64bits register
                                // we left shift the value, then arithmetic right shift back
                                let from_ty_len = extract_int_len(from_ty);
                                let to_ty_len   = extract_int_len(to_ty);

                                let shift : i8 = (to_ty_len - from_ty_len) as i8;

                                if self.match_ireg(op) {
                                    let tmp_op = self.emit_ireg(op, f_content, f_context, vm);
                                    let tmp_res = self.get_result_value(node);

                                    // mov op -> result
                                    self.backend.emit_mov_r64_r64(&tmp_res, &tmp_op);

                                    // shl result, shift -> result
                                    self.backend.emit_shl_r64_imm8(&tmp_res, shift);

                                    // sar result, shift -> result
                                    self.backend.emit_sar_r64_imm8(&tmp_res, shift);
                                } else {
                                    panic!("unexpected op (expect ireg): {}", op)
                                }
                            }

                            _ => unimplemented!()
                        }
                    }
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                    // load on x64 generates mov inst (no matter what order is specified)
                    // https://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
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                    Instruction_::Load{is_ptr, order, mem_loc} => {
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                        let ops = inst.ops.read().unwrap();
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                        let ref loc_op = ops[mem_loc];
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                        // check order
                        match order {
                            MemoryOrder::Relaxed 
                            | MemoryOrder::Consume 
                            | MemoryOrder::Acquire
                            | MemoryOrder::SeqCst => {},
                            _ => panic!("didnt expect order {:?} with store inst", order)
                        }                        
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                        let resolved_loc = self.emit_node_addr_to_value(loc_op, vm);
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                        let res_temp = self.get_result_value(node);
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                        if self.match_ireg(node) {
                            // emit mov(GPR)
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                            self.backend.emit_mov_r64_mem64(&res_temp, &resolved_loc);
                        } else {
                            // emit mov(FPR)
                            unimplemented!()
                        }
                    }
                    
                    Instruction_::Store{is_ptr, order, mem_loc, value} => {
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                        let ops = inst.ops.read().unwrap();
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                        let ref loc_op = ops[mem_loc];
                        let ref val_op = ops[value];
                        
                        let generate_plain_mov : bool = {
                            match order {
                                MemoryOrder::Relaxed | MemoryOrder::Release => true,
                                MemoryOrder::SeqCst => false,
                                _ => panic!("didnt expect order {:?} with store inst", order)
                            }
                        };
                        
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                        let resolved_loc = self.emit_node_addr_to_value(loc_op, vm);
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                        if self.match_ireg(val_op) {
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                            let val = self.emit_ireg(val_op, f_content, f_context, vm);
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                            if generate_plain_mov {
                                self.backend.emit_mov_mem64_r64(&resolved_loc, &val);
                            } else {
                                unimplemented!()
                            }
                        } else if self.match_iimm(val_op) {
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                            let val = self.node_iimm_to_i32(val_op);
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                            if generate_plain_mov {
                                self.backend.emit_mov_mem64_imm32(&resolved_loc, val);
                            } else {
                                unimplemented!()
                            }
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                        } else {
                            // emit mov(FPR)
                            unimplemented!()
                        }
                    }
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                    Instruction_::GetIRef(op_index) => {
                        let ops = inst.ops.read().unwrap();
                        
                        let ref op = ops[op_index];
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                        let res_tmp = self.get_result_value(node);
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                        let hdr_size = mm::objectmodel::OBJECT_HEADER_SIZE;
                        if hdr_size == 0 {
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                            self.emit_move_node_to_value(&res_tmp, &op, f_content, f_context, vm);
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                        } else {
                            self.emit_lea_base_offset(&res_tmp, &op.clone_value(), hdr_size as i32, vm);
                        }
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                    }
                    
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                    Instruction_::ThreadExit => {
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                        // emit a call to swap_back_to_native_stack(sp_loc: Address)
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                        // get thread local and add offset to get sp_loc
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                        let tl = self.emit_get_threadlocal(Some(node), f_content, f_context, vm);
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                        self.backend.emit_add_r64_imm32(&tl, *thread::NATIVE_SP_LOC_OFFSET as i32);
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                        self.emit_runtime_entry(&entrypoints::SWAP_BACK_TO_NATIVE_STACK, vec![tl.clone()], None, Some(node), f_content, f_context, vm);
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                    }
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                    Instruction_::New(ref ty) => {
                        let ty_info = vm.get_backend_type_info(ty.id());
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                        let ty_size = ty_info.size;
                        let ty_align= ty_info.alignment;
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                        if ty_size > mm::LARGE_OBJECT_THRESHOLD {
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                            // emit large object allocation
                            unimplemented!()
                        } else {
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                            // emit immix allocation fast path
                            
                            // ASM: %tl = get_thread_local()
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                            let tmp_tl = self.emit_get_threadlocal(Some(node), f_content, f_context, vm);
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                            // ASM: mov [%tl + allocator_offset + cursor_offset] -> %cursor
                            let cursor_offset = *thread::ALLOCATOR_OFFSET + *mm::ALLOCATOR_CURSOR_OFFSET;
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                            let tmp_cursor = self.make_temporary(f_context, ADDRESS_TYPE.clone(), vm);
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                            self.emit_load_base_offset(&tmp_cursor, &tmp_tl, cursor_offset as i32, vm);
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                            // alignup cursor (cursor + align - 1 & !(align - 1))
                            // ASM: lea align-1(%cursor) -> %start
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                            let align = ty_info.alignment as i32;
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                            let tmp_start = self.make_temporary(f_context, ADDRESS_TYPE.clone(), vm);
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                            self.emit_lea_base_offset(&tmp_start, &tmp_cursor, align - 1, vm);
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                            // ASM: and %start, !(align-1) -> %start
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                            self.backend.emit_and_r64_imm32(&tmp_start, !(align - 1) as i32);
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                            // bump cursor
                            // ASM: lea size(%start) -> %end
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                            let tmp_end = self.make_temporary(f_context, ADDRESS_TYPE.clone(), vm);
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                            self.emit_lea_base_offset(&tmp_end, &tmp_start, ty_size as i32, vm);
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                            // check with limit
                            // ASM: cmp %end, [%tl + allocator_offset + limit_offset]
                            let limit_offset = *thread::ALLOCATOR_OFFSET + *mm::ALLOCATOR_LIMIT_OFFSET;
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                            let mem_limit = self.make_memory_op_base_offset(&tmp_tl, limit_offset as i32, ADDRESS_TYPE.clone(), vm);
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                            self.backend.emit_cmp_mem64_r64(&mem_limit, &tmp_end);
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                            // branch to slow path if end > limit (end - limit > 0)
                            // ASM: jg alloc_slow
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                            let slowpath = format!("{}_allocslow", node.id());
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                            self.backend.emit_jg(slowpath.clone());
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                            // update cursor
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                            // ASM: mov %end -> [%tl + allocator_offset + cursor_offset]
                            self.emit_store_base_offset(&tmp_tl, cursor_offset as i32, &tmp_end, vm);
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                            // put start as result
                            // ASM: mov %start -> %result
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                            let tmp_res = self.get_result_value(node);
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                            self.backend.emit_mov_r64_r64(&tmp_res, &tmp_start);
                            
                            // ASM jmp alloc_end
                            let allocend = format!("{}_allocend", node.id());
                            self.backend.emit_jmp(allocend.clone());
                            
                            // finishing current block
                            self.backend.end_block(self.current_block.as_ref().unwrap().clone());
                            
                            // alloc_slow: 
                            // call alloc_slow(size, align) -> %ret
                            // new block (no livein)
                            self.current_block = Some(slowpath.clone());
                            self.backend.start_block(slowpath.clone());
                            self.backend.set_block_livein(slowpath.clone(), &vec![]); 
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                            // arg1: allocator address                            
                            let allocator_offset = *thread::ALLOCATOR_OFFSET;
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                            let tmp_allocator = self.make_temporary(f_context, ADDRESS_TYPE.clone(), vm);
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                            self.emit_lea_base_offset(&tmp_allocator, &tmp_tl, allocator_offset as i32, vm);
                            // arg2: size                            
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                            let const_size = self.make_value_int_const(ty_size as u64, vm);
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                            // arg3: align
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                            let const_align= self.make_value_int_const(ty_align as u64, vm);
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                            let rets = self.emit_runtime_entry(
                                &entrypoints::ALLOC_SLOW,
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                                vec![tmp_allocator, const_size, const_align],
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                                Some(vec![
                                    tmp_res.clone()
                                ]),
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                                Some(node), f_content, f_context, vm
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                            );
                            
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                            // end block (no liveout other than result)
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                            self.backend.end_block(slowpath.clone());
                            self.backend.set_block_liveout(slowpath.clone(), &vec![tmp_res.clone()]);
                            
                            // block: alloc_end
                            self.backend.start_block(allocend.clone());
                            self.current_block = Some(allocend.clone());
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                        }
                    }
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                    Instruction_::Throw(op_index) => {
                        let ops = inst.ops.read().unwrap();
                        let ref exception_obj = ops[op_index];
                        
                        self.emit_runtime_entry(
                            &entrypoints::THROW_EXCEPTION, 
                            vec![exception_obj.clone_value()], 
                            None,
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                            Some(node), f_content, f_context, vm);
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                    }
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                    _ => unimplemented!()
                } // main switch
            },
            
            TreeNode_::Value(ref p) => {
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            }
        }
    }
    
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    fn make_temporary(&mut self, f_context: &mut FunctionContext, ty: P<MuType>, vm: &VM) -> P<Value> {
        f_context.make_temporary(vm.next_id(), ty).clone_value()
    }
    
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    fn make_memory_op_base_offset (&mut self, base: &P<Value>, offset: i32, ty: P<MuType>, vm: &VM) -> P<Value> {
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        P(Value{
            hdr: MuEntityHeader::unnamed(vm.next_id()),
            ty: ty.clone(),
            v: Value_::Memory(MemoryLocation::Address{
                base: base.clone(),
                offset: Some(self.make_value_int_const(offset as u64, vm)),
                index: None,
                scale: None
            })
        })
    }
    
    fn make_value_int_const (&mut self, val: u64, vm: &VM) -> P<Value> {
        P(Value{
            hdr: MuEntityHeader::unnamed(vm.next_id()),
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            ty: UINT64_TYPE.clone(),
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            v: Value_::Constant(Constant::Int(val))
        })
    } 
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    fn emit_truncate_result (&mut self, from_ty: &P<MuType>, to_ty: &P<MuType>, op: &P<Value>, f_context: &mut FunctionContext, vm: &VM) {
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        // currently only use 64bits register
        // so only keep what is needed in the register (set others to 0)
        let from_ty_len = match from_ty.v {
            MuType_::Int(len) => len,
            _ => panic!("only expect int types, found: {}", from_ty)
        };
        let to_ty_len   = match to_ty.v {
            MuType_::Int(len) => len,
            _ => panic!("only expect int types, found: {}", to_ty)
        };

        if from_ty_len == to_ty_len {
            return;
        } else {
            debug_assert!(from_ty_len > to_ty_len);

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            if to_ty_len < 32 {
                // ignoring from_ty for now (we use 64bits register for everything)
                let mask = match to_ty_len {
                    8 => 0xFFi32,
                    16 => 0xFFFFi32,
                    _ => unimplemented!()
                };

                // and mask, result -> result
                self.backend.emit_and_r64_imm32(&op, mask);
            } else if to_ty_len == 32 {
                let tmp_mask = self.make_temporary(f_context, UINT64_TYPE.clone(), vm);
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                self.backend.emit_mov_r64_imm64(&tmp_mask, 0xFFFFFFFF as i64);

                self.backend.emit_and_r64_r64(&op, &tmp_mask);
            } else {
                unimplemented!()
            }
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        }
    }

    fn emit_sign_extend_operand (&mut self, from_ty: &P<MuType>, to_ty: &P<MuType>, op: &P<Value>) {
        // currently only use 64bits register
        // we left shift the value, then arithmetic right shift back
        let from_ty_len = match from_ty.v {
            MuType_::Int(len) => len,
            _ => panic!("only expect int types, found: {}", from_ty)
        };
        let to_ty_len   = match to_ty.v {
            MuType_::Int(len) => len,
            _ => panic!("only expect int types, found: {}", to_ty)
        };

        if from_ty_len == to_ty_len {
            return;
        } else {
            debug_assert!(to_ty_len > from_ty_len);

            let shift : i8 = (to_ty_len - from_ty_len) as i8;

            // shl result, shift -> result
            self.backend.emit_shl_r64_imm8(&op, shift);
            // sar result, shift -> result
            self.backend.emit_sar_r64_imm8(&op, shift);
        }
    }

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    fn emit_load_base_offset (&mut self, dest: &P<Value>, base: &P<Value>, offset: i32, vm: &VM) {
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        let mem = self.make_memory_op_base_offset(base, offset, dest.ty.clone(), vm);
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        if dest.is_int_reg() {
            self.backend.emit_mov_r64_mem64(dest, &mem);
        } else if dest.is_fp_reg() {
            self.backend.emit_movsd_f64_mem64(dest, &mem);
        } else {
            unimplemented!();
        }
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    }
    
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    fn emit_store_base_offset (&mut self, base: &P<Value>, offset: i32, src: &P<Value>, vm: &VM) {
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        let mem = self.make_memory_op_base_offset(base, offset, src.ty.clone(), vm);
        
        self.backend.emit_mov_mem64_r64(&mem, src);
    }
    
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    fn emit_lea_base_offset (&mut self, dest: &P<Value>, base: &P<Value>, offset: i32, vm: &VM) {
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        let mem = self.make_memory_op_base_offset(base, offset, ADDRESS_TYPE.clone(), vm);
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        self.backend.emit_lea_r64(dest, &mem);
    }
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    fn emit_udiv (
        &mut self,
        op1: &P<TreeNode>, op2: &P<TreeNode>,
        f_content: &FunctionContent,
        f_context: &mut FunctionContext,
        vm: &VM)
    {
        let rax = x86_64::RAX.clone();
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        debug_assert!(self.match_ireg(op1));
        let reg_op1 = self.emit_ireg(op1, f_content, f_context, vm);
        self.emit_move_value_to_value(&rax, &reg_op1);
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        // xorq rdx, rdx -> rdx
        let rdx = x86_64::RDX.clone();
        self.backend.emit_xor_r64_r64(&rdx, &rdx);

        // div op2
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        if self.match_mem(op2) {
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            let mem_op2 = self.emit_mem(op2, vm);
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            self.backend.emit_div_mem64(&mem_op2);
        } else if self.match_iimm(op2) {
            let imm = self.node_iimm_to_i32(op2);
            // moving to a temp
            let temp = self.make_temporary(f_context, UINT64_TYPE.clone(), vm);
            self.backend.emit_mov_r64_imm32(&temp, imm);

            // div tmp
            self.backend.emit_div_r64(&temp);
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        } else if self.match_ireg(op2) {
            let reg_op2 = self.emit_ireg(op2, f_content, f_context, vm);

            self.backend.emit_div_r64(&reg_op2);
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        } else {
            unimplemented!();
        }
    }

    fn emit_idiv (
        &mut self,
        op1: &P<TreeNode>, op2: &P<TreeNode>,
        f_content: &FunctionContent,
        f_context: &mut FunctionContext,
        vm: &VM)
    {
        let rax = x86_64::RAX.clone();
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        debug_assert!(self.match_ireg(op1));
        let reg_op1 = self.emit_ireg(op1, f_content, f_context, vm);
        self.emit_move_value_to_value(&rax, &reg_op1);
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        // sign extend rax
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        self.emit_sign_extend_operand(&reg_op1.ty, &UINT64_TYPE, &rax);
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        // cqo
        self.backend.emit_cqo();

        // idiv op2
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        if self.match_mem(op2) {
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            let mem_op2 = self.emit_mem(op2, vm);
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            self.backend.emit_idiv_mem64(&mem_op2);
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            // need to sign extend op2
            unimplemented!()
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        } else if self.match_iimm(op2) {
            let imm = self.node_iimm_to_i32(op2);
            // moving to a temp
            let temp = self.make_temporary(f_context, UINT64_TYPE.clone(), vm);
            self.backend.emit_mov_r64_imm32(&temp, imm);

            // idiv temp
            self.backend.emit_idiv_r64(&temp);
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        } else if self.match_ireg(op2) {
            let reg_op2 = self.emit_ireg(op2, f_content, f_context, vm);

            self.emit_sign_extend_operand(&reg_op2.ty, &UINT64_TYPE, &reg_op2);

            self.backend.emit_idiv_r64(&reg_op2);
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        } else {
            unimplemented!();
        }
    }
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    fn emit_get_threadlocal (
        &mut self, 
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        cur_node: Option<&TreeNode>,
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        f_content: &FunctionContent, 
        f_context: &mut FunctionContext, 
        vm: &VM) -> P<Value> {
        let mut rets = self.emit_runtime_entry(&entrypoints::GET_THREAD_LOCAL, vec![], None, cur_node, f_content, f_context, vm);
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        rets.pop().unwrap()
    }
    
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    // ret: Option<Vec<P<Value>>
    // if ret is Some, return values will put stored in given temporaries
    // otherwise create temporaries
    // always returns result temporaries (given or created)
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    fn emit_runtime_entry (
        &mut self, 
        entry: &RuntimeEntrypoint, 
        args: Vec<P<Value>>, 
        rets: Option<Vec<P<Value>>>,
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        cur_node: Option<&TreeNode>, 
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        f_content: &FunctionContent, 
        f_context: &mut FunctionContext, 
        vm: &VM) -> Vec<P<Value>> {
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        let sig = entry.sig.clone();
        
        let entry_name = {
            if vm.is_running() {
                unimplemented!()
            } else {
                let ref entry_loc = entry.aot;
                
                match entry_loc {
                    &ValueLocation::Relocatable(_, ref name) => name.clone(),
                    _ => panic!("expecting a relocatable value")
                }
            }
        };
        
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        self.emit_c_call(entry_name, sig, args, rets, cur_node, f_content, f_context, vm)
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    }
    
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    // returns the stack arg offset - we will need this to collapse stack after the call
    fn emit_precall_convention(
        &mut self,
        args: &Vec<P<Value>>, 
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        vm: &VM) -> usize {
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        // if we need to save caller saved regs
        // put it here (since this is fastpath compile, we wont have them)
        
        // put args into registers if we can
        // in the meantime record args that do not fit in registers
        let mut stack_args : Vec<P<Value>> = vec![];        
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        let mut gpr_arg_count = 0;
        for arg in args.iter() {
            if arg.is_int_reg() {
                if gpr_arg_count < x86_64::ARGUMENT_GPRs.len() {
                    self.backend.emit_mov_r64_r64(&x86_64::ARGUMENT_GPRs[gpr_arg_count], &arg);
                    gpr_arg_count += 1;
                } else {
                    // use stack to pass argument
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                    stack_args.push(arg.clone());
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                }
            } else if arg.is_int_const() {
                if x86_64::is_valid_x86_imm(arg) {                
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                    let int_const = arg.extract_int_const() as i32;
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                    if gpr_arg_count < x86_64::ARGUMENT_GPRs.len() {
                        self.backend.emit_mov_r64_imm32(&x86_64::ARGUMENT_GPRs[gpr_arg_count], int_const);
                        gpr_arg_count += 1;
                    } else {
                        // use stack to pass argument
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                        stack_args.push(arg.clone());
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                    }
                } else {
                    // put the constant to memory
                    unimplemented!()
                }
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            } else if arg.is_mem() {
                if gpr_arg_count < x86_64::ARGUMENT_GPRs.len() {
                    self.backend.emit_mov_r64_mem64(&x86_64::