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asm_backend.rs 120 KB
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// Copyright 2017 The Australian National University
// 
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
// 
//     http://www.apache.org/licenses/LICENSE-2.0
// 
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.

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use compiler::backend::AOT_EMIT_CONTEXT_FILE;
use compiler::backend::RegGroup;
use utils::ByteSize;
use utils::Address;
use utils::POINTER_SIZE;
use compiler::backend::aarch64::*;

use compiler::backend::{Reg, Mem};
use compiler::machine_code::MachineCode;
use vm::VM;
use runtime::ValueLocation;

use utils::vec_utils;
use utils::string_utils;
use utils::LinkedHashMap;

use ast::ptr::P;
use ast::ir::*;
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use ast::types;
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use std::str;
use std::usize;
use std::ops;
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use std::collections::HashSet;
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use std::sync::RwLock;
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struct ASMCode {
    name: MuName,
    code: Vec<ASMInst>,

    entry:  MuName,
    blocks: LinkedHashMap<MuName, ASMBlock>,

    frame_size_patchpoints: Vec<ASMLocation>
}

unsafe impl Send for ASMCode {}
unsafe impl Sync for ASMCode {}

impl ASMCode {
    fn get_use_locations(&self, reg: MuID) -> Vec<ASMLocation> {
        let mut ret = vec![];

        for inst in self.code.iter() {
            match inst.uses.get(&reg) {
                Some(ref locs) => {
                    ret.append(&mut locs.to_vec());
                },
                None => {}
            }
        }

        ret
    }

    fn get_define_locations(&self, reg: MuID) -> Vec<ASMLocation> {
        let mut ret = vec![];

        for inst in self.code.iter() {
            match inst.defines.get(&reg) {
                Some(ref locs) => {
                    ret.append(&mut locs.to_vec());
                },
                None => {}
            }
        }

        ret
    }

    fn is_block_start(&self, inst: usize) -> bool {
        for block in self.blocks.values() {
            if block.start_inst == inst {
                return true;
            }
        }
        false
    }

    fn is_last_inst_in_block(&self, inst: usize) -> bool {
        for block in self.blocks.values() {
            if block.end_inst == inst + 1 {
                return true;
            }
        }
        false
    }

    fn get_block_by_inst(&self, inst: usize) -> (&String, &ASMBlock) {
        for (name, block) in self.blocks.iter() {
            if inst >= block.start_inst && inst < block.end_inst {
                return (name, block);
            }
        }

        panic!("didnt find any block for inst {}", inst)
    }

    fn rewrite_insert(
        &self,
        insert_before: LinkedHashMap<usize, Vec<Box<ASMCode>>>,
        insert_after: LinkedHashMap<usize, Vec<Box<ASMCode>>>) -> Box<ASMCode>
    {
        trace!("insert spilling code");
        let mut ret = ASMCode {
            name: self.name.clone(),
            entry: self.entry.clone(),
            code: vec![],
            blocks: linked_hashmap!{},
            frame_size_patchpoints: vec![]
        };

        // iterate through old machine code
        let mut inst_offset = 0;    // how many instructions has been inserted
        let mut cur_block_start = usize::MAX;

        // inst N in old machine code is N' in new machine code
        // this map stores the relationship
        let mut location_map : LinkedHashMap<usize, usize> = LinkedHashMap::new();

        for i in 0..self.number_of_insts() {
            trace!("Inst{}", i);

            if self.is_block_start(i) {
                cur_block_start = i + inst_offset;
                trace!("  block start is shifted to {}", cur_block_start);
            }

            // insert code before this instruction
            if insert_before.contains_key(&i) {
                for insert in insert_before.get(&i).unwrap() {
                    ret.append_code_sequence_all(insert);
                    inst_offset += insert.number_of_insts();
                    trace!("  inserted {} insts before", insert.number_of_insts());
                }
            }

            // copy this instruction
            let mut inst = self.code[i].clone();

            // old ith inst is now the (i + inst_offset)th instruction
            location_map.insert(i, i + inst_offset);
            trace!("  Inst{} is now Inst{}", i, i + inst_offset);

            // this instruction has been offset by several instructions('inst_offset')
            // update its info
            // 1. fix defines and uses
            for locs in inst.defines.values_mut() {
                for loc in locs {
                    debug_assert!(loc.line == i);
                    loc.line += inst_offset;
                }
            }
            for locs in inst.uses.values_mut() {
                for loc in locs {
                    debug_assert!(loc.line == i);
                    loc.line += inst_offset;
                }
            }
            // 2. we need to delete existing preds/succs - CFA is required later
            inst.preds.clear();
            inst.succs.clear();
            // 3. add the inst
            ret.code.push(inst);


            // insert code after this instruction
            if insert_after.contains_key(&i) {
                for insert in insert_after.get(&i).unwrap() {
                    ret.append_code_sequence_all(insert);
                    inst_offset += insert.number_of_insts();
                    trace!("  inserted {} insts after", insert.number_of_insts());
                }
            }

            if self.is_last_inst_in_block(i) {
                let cur_block_end = i + 1 + inst_offset;

                // copy the block
                let (name, block) = self.get_block_by_inst(i);

                let new_block = ASMBlock{
                    start_inst: cur_block_start,
                    end_inst: cur_block_end,

                    livein: vec![],
                    liveout: vec![]
                };

                trace!("  old block: {:?}", block);
                trace!("  new block: {:?}", new_block);

                cur_block_start = usize::MAX;

                // add to the new code
                ret.blocks.insert(name.clone(), new_block);
            }
        }

        // fix patchpoint
        for patchpoint in self.frame_size_patchpoints.iter() {
            let new_patchpoint = ASMLocation {
                line: *location_map.get(&patchpoint.line).unwrap(),
                index: patchpoint.index,
                len: patchpoint.len,
                oplen: patchpoint.oplen
            };

            ret.frame_size_patchpoints.push(new_patchpoint);
        }

        ret.control_flow_analysis();

        Box::new(ret)
    }

    fn append_code_sequence(
        &mut self,
        another: &Box<ASMCode>,
        start_inst: usize,
        n_insts: usize)
    {
        let base_line = self.number_of_insts();

        for i in 0..n_insts {
            let cur_line_in_self = base_line + i;
            let cur_line_from_copy = start_inst + i;

            let mut inst = another.code[cur_line_from_copy].clone();

            // fix info
            for locs in inst.defines.values_mut() {
                for loc in locs {
                    debug_assert!(loc.line == i);
                    loc.line = cur_line_in_self;
                }
            }
            for locs in inst.uses.values_mut() {
                for loc in locs {
                    debug_assert!(loc.line == i);
                    loc.line = cur_line_in_self;
                }
            }
            // ignore preds/succs

            // add to self
            self.code.push(inst);
        }
    }

    fn append_code_sequence_all(&mut self, another: &Box<ASMCode>) {
        let n_insts = another.number_of_insts();
        self.append_code_sequence(another, 0, n_insts)
    }

    fn control_flow_analysis(&mut self) {
        const TRACE_CFA : bool = true;

        // control flow analysis
        let n_insts = self.number_of_insts();

        let ref mut asm = self.code;

        for i in 0..n_insts {
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            trace_if!(TRACE_CFA, "---inst {}---", i);
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            // skip symbol
            if asm[i].is_symbol {
                continue;
            }

            // determine predecessor

            // we check if it is a fallthrough block
            if i != 0 {
                let last_inst = ASMCode::find_prev_inst(i, asm);

                match last_inst {
                    Some(last_inst) => {
                        let last_inst_branch = asm[last_inst].branch.clone();
                        match last_inst_branch {
                            // if it is a fallthrough, we set its preds as last inst
                            ASMBranchTarget::None => {
                                if !asm[i].preds.contains(&last_inst) {
                                    asm[i].preds.push(last_inst);

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                                    trace_if!(TRACE_CFA, "inst {}: set PREDS as previous inst - fallthrough {}", i, last_inst);
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                                }
                            }
                            // otherwise do nothing
                            _ => {}
                        }
                    }
                    None => {}
                }
            }

            // determine successor
            let branch = asm[i].branch.clone();
            match branch {
                ASMBranchTarget::Unconditional(ref target) => {
                    // branch to target
                    let target_n = self.blocks.get(target).unwrap().start_inst;

                    // cur inst's succ is target
                    asm[i].succs.push(target_n);

                    // target's pred is cur
                    asm[target_n].preds.push(i);

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                    trace_if!(TRACE_CFA, "inst {}: is a branch to {}", i, target);
                    trace_if!(TRACE_CFA, "inst {}: branch target index is {}", i, target_n);
                    trace_if!(TRACE_CFA, "inst {}: set SUCCS as branch target {}", i, target_n);
                    trace_if!(TRACE_CFA, "inst {}: set PREDS as branch source {}", target_n, i);
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                },
                ASMBranchTarget::Conditional(ref target) => {
                    // branch to target
                    let target_n = self.blocks.get(target).unwrap().start_inst;

                    // cur insts' succ is target
                    asm[i].succs.push(target_n);

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                    trace_if!(TRACE_CFA, "inst {}: is a cond branch to {}", i, target);
                    trace_if!(TRACE_CFA, "inst {}: branch target index is {}", i, target_n);
                    trace_if!(TRACE_CFA, "inst {}: set SUCCS as branch target {}", i, target_n);
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                    // target's pred is cur
                    asm[target_n].preds.push(i);
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                    trace_if!(TRACE_CFA, "inst {}: set PREDS as {}", target_n, i);
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                    if let Some(next_inst) = ASMCode::find_next_inst(i, asm) {
                        // cur succ is next inst
                        asm[i].succs.push(next_inst);

                        // next inst's pred is cur
                        asm[next_inst].preds.push(i);

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                        trace_if!(TRACE_CFA, "inst {}: SET SUCCS as c-branch fallthrough target {}", i, next_inst);
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                    } else {
                        panic!("conditional branch does not have a fallthrough target");
                    }
                },
                ASMBranchTarget::PotentiallyExcepting(ref target) => {
                    // may trigger exception and jump to target - similar as conditional branch
                    let target_n = self.blocks.get(target).unwrap().start_inst;

                    // cur inst's succ is target
                    asm[i].succs.push(target_n);

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                    trace_if!(TRACE_CFA, "inst {}: is potentially excepting to {}", i, target);
                    trace_if!(TRACE_CFA, "inst {}: excepting target index is {}", i, target_n);
                    trace_if!(TRACE_CFA, "inst {}: set SUCCS as excepting target {}", i, target_n);
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                    asm[target_n].preds.push(i);

                    if let Some(next_inst) = ASMCode::find_next_inst(i, asm) {
                        // cur succ is next inst
                        asm[i].succs.push(next_inst);

                        // next inst's pred is cur
                        asm[next_inst].preds.push(i);

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                        trace_if!(TRACE_CFA, "inst {}: SET SUCCS as PEI fallthrough target {}", i, next_inst);
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                    } else {
                        panic!("PEI does not have a fallthrough target");
                    }
                },
                ASMBranchTarget::Return => {
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                    trace_if!(TRACE_CFA, "inst {}: is a return", i);
                    trace_if!(TRACE_CFA, "inst {}: has no successor", i);
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                }
                ASMBranchTarget::None => {
                    // not branch nor cond branch, succ is next inst
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                    trace_if!(TRACE_CFA, "inst {}: not a branch inst", i);
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                    if let Some(next_inst) = ASMCode::find_next_inst(i, asm) {
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                        trace_if!(TRACE_CFA, "inst {}: set SUCCS as next inst {}", i, next_inst);
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                        asm[i].succs.push(next_inst);
                    }
                }
                ASMBranchTarget::UnconditionalReg(id) => {
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                    trace_if!(TRACE_CFA, "inst {}: is an unconditional branch to reg {}", i, id);
                    trace_if!(TRACE_CFA, "inst {}: has no successor", i);
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                }
            }
        }
    }

    fn find_prev_inst(i: usize, asm: &Vec<ASMInst>) -> Option<usize> {
        if i == 0 {
            None
        } else {
            let mut cur = i - 1;
            while cur != 0 {
                if !asm[cur].is_symbol {
                    return Some(cur);
                }

                if cur == 0 {
                    return None;
                } else {
                    cur -= 1;
                }
            }

            None
        }
    }

    fn find_next_inst(i: usize, asm: &Vec<ASMInst>) -> Option<usize> {
        if i >= asm.len() - 1 {
            None
        } else {
            let mut cur = i + 1;
            while cur < asm.len() {
                if !asm[cur].is_symbol {
                    return Some(cur);
                }

                cur += 1;
            }

            None
        }
    }

    fn find_last_inst(i: usize, asm: &Vec<ASMInst>) -> Option<usize> {
        if i == 0 {
            None
        } else {
            let mut cur = i;
            loop {
                if !asm[cur].is_symbol {
                    return Some(cur);
                }

                if cur == 0 {
                    return None;
                } else {
                    cur -= 1;
                }
            }
        }
    }

    fn add_frame_size_patchpoint(&mut self, patchpoint: ASMLocation) {
        self.frame_size_patchpoints.push(patchpoint);
    }
}

use std::any::Any;

impl MachineCode for ASMCode {
    fn as_any(&self) -> &Any {
        self
    }
    fn number_of_insts(&self) -> usize {
        self.code.len()
    }

    fn is_move(&self, index: usize) -> bool {
        let inst = self.code.get(index);
        match inst {
            Some(inst) => {
                let ref inst = inst.code;

                if inst.starts_with("MOV ") || inst.starts_with("FMOV ") {
                    // normal mov
                    true
                } else {
                    false
                }
            },
            None => false
        }
    }

    fn is_using_mem_op(&self, index: usize) -> bool {
        self.code[index].is_mem_op_used
    }

    fn is_jmp(&self, index: usize) -> Option<MuName> {
        let inst = self.code.get(index);
        match inst {
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            Some(inst) if inst.code.starts_with("B.") || inst.code.starts_with("B ") => {
                // Destination is the first argument
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                let split : Vec<&str> = inst.code.split(' ').collect();
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                Some(demangle_name(String::from(split[1])))
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            }
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            Some(inst) if inst.code.starts_with("CBNZ ")  || inst.code.starts_with("CBZ ") => {
                // Destination is the second argument
                let split : Vec<&str> = inst.code.split(',').collect();
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                Some(demangle_name(String::from(split[1])))
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            }
            Some(inst) if inst.code.starts_with("TBNZ ")  || inst.code.starts_with("TBZ ") => {
                // Destination is the third argument
                let split : Vec<&str> = inst.code.split(',').collect();
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                Some(demangle_name(String::from(split[2])))
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            }

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            _ => None
        }
    }

    fn is_label(&self, index: usize) -> Option<MuName> {
        let inst = self.code.get(index);
        match inst {
            Some(inst) if inst.code.ends_with(':') => {
                let split : Vec<&str> = inst.code.split(':').collect();

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                Some(demangle_name(String::from(split[0])))
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            }
            _ => None
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    }

    fn is_spill_load(&self, index: usize) -> Option<P<Value>> {
        if let Some(inst) = self.code.get(index) {
            match inst.spill_info {
                Some(SpillMemInfo::Load(ref p)) => Some(p.clone()),
                _ => None
            }
        } else {
            None
        }
    }

    fn is_spill_store(&self, index: usize) -> Option<P<Value>> {
        if let Some(inst) = self.code.get(index) {
            match inst.spill_info {
                Some(SpillMemInfo::Store(ref p)) => Some(p.clone()),
                _ => None
            }
        } else {
            None
        }
    }

    fn get_succs(&self, index: usize) -> &Vec<usize> {
        &self.code[index].succs
    }

    fn get_preds(&self, index: usize) -> &Vec<usize> {
        &self.code[index].preds
    }

    fn get_inst_reg_uses(&self, index: usize) -> Vec<MuID> {
        self.code[index].uses.keys().map(|x| *x).collect()
    }

    fn get_inst_reg_defines(&self, index: usize) -> Vec<MuID> {
        self.code[index].defines.keys().map(|x| *x).collect()
    }

    fn replace_reg(&mut self, from: MuID, to: MuID) {
        for loc in self.get_define_locations(from) {
            let ref mut inst_to_patch = self.code[loc.line];

            // pick the right reg based on length
            let to_reg = get_alias_for_length(to, loc.oplen);
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            let to_reg_string = to_reg.name();
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            string_utils::replace(&mut inst_to_patch.code, loc.index, &to_reg_string, to_reg_string.len());
        }

        for loc in self.get_use_locations(from) {
            let ref mut inst_to_patch = self.code[loc.line];

            // pick the right reg based on length
            let to_reg = get_alias_for_length(to, loc.oplen);
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            let to_reg_string = to_reg.name();
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            string_utils::replace(&mut inst_to_patch.code, loc.index, &to_reg_string, to_reg_string.len());
        }
    }

    fn replace_define_tmp_for_inst(&mut self, from: MuID, to: MuID, inst: usize) {
        let to_reg_string : MuName = REG_PLACEHOLDER.clone();

        let asm = &mut self.code[inst];
        // if this reg is defined, replace the define
        if asm.defines.contains_key(&from) {
            let define_locs = asm.defines.get(&from).unwrap().to_vec();
            // replace temps
            for loc in define_locs.iter() {
                string_utils::replace(&mut asm.code, loc.index, &to_reg_string, to_reg_string.len());
            }

            // remove old key, insert new one
            asm.defines.remove(&from);
            asm.defines.insert(to, define_locs);
        }
    }

    fn replace_use_tmp_for_inst(&mut self, from: MuID, to: MuID, inst: usize) {
        let to_reg_string : MuName = REG_PLACEHOLDER.clone();

        let asm = &mut self.code[inst];

        // if this reg is used, replace the use
        if asm.uses.contains_key(&from) {
            let use_locs = asm.uses.get(&from).unwrap().to_vec();
            // replace temps
            for loc in use_locs.iter() {
                string_utils::replace(&mut asm.code, loc.index, &to_reg_string, to_reg_string.len());
            }

            // remove old key, insert new one
            asm.uses.remove(&from);
            asm.uses.insert(to, use_locs);
        }
    }

    fn set_inst_nop(&mut self, index: usize) {
        self.code[index].code.clear();
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        //        self.code.remove(index);
        //        self.code.insert(index, ASMInst::nop());
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    }

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    fn remove_unnecessary_callee_saved(&mut self, used_callee_saved: Vec<MuID>) -> HashSet<MuID> {
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        // every push pair (STP)/and pop pair (LDP) will use/define SP
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        let fp = FP.extract_ssa_id().unwrap();
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        // Note: this version assumes only 1 callee is pushed or poped
        let find_op_other_than_fp = |inst: &ASMInst| -> MuID {
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            for id in inst.defines.keys() {
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                if *id != fp {
                    return *id;
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                }
            }
            for id in inst.uses.keys() {
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                if *id != fp {
                    return *id;
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                }
            }

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            panic!("Expected to find a used register other than the FP");
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        };

        let mut inst_to_remove = vec![];
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        let mut regs_to_remove = HashSet::new();
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        for i in 0..self.number_of_insts() {
            let ref inst = self.code[i];

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            match inst.spill_info {
                Some(SpillMemInfo::CalleeSaved) => {
                    let reg = find_op_other_than_fp(inst);
                    if !used_callee_saved.contains(&reg) {
                        inst_to_remove.push(i);
                        regs_to_remove.insert(reg);
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                    }
                }
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                _ => {}
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            }
        }

        for i in inst_to_remove {
            self.set_inst_nop(i);
        }
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        regs_to_remove
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    }

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    fn patch_frame_size(&mut self, size: usize) {
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        debug_assert!(size % 16 == 0);

        let size = size.to_string();

        debug_assert!(size.len() <= FRAME_SIZE_PLACEHOLDER_LEN);

        for loc in self.frame_size_patchpoints.iter() {
            let ref mut inst = self.code[loc.line];

            string_utils::replace(&mut inst.code, loc.index, &size, size.len());
        }
    }

    fn emit(&self) -> Vec<u8> {
        let mut ret = vec![];

        for inst in self.code.iter() {
            if !inst.is_symbol {
                ret.append(&mut "\t".to_string().into_bytes());
            }

            ret.append(&mut inst.code.clone().into_bytes());
            ret.append(&mut "\n".to_string().into_bytes());
        }

        ret
    }

    fn emit_inst(&self, index: usize) -> Vec<u8> {
        let mut ret = vec![];

        let ref inst = self.code[index];

        if !inst.is_symbol {
            ret.append(&mut "\t".to_string().into_bytes());
        }

        ret.append(&mut inst.code.clone().into_bytes());

        ret
    }

    fn trace_mc(&self) {
        trace!("");

        trace!("code for {}: \n", self.name);

        let n_insts = self.code.len();
        for i in 0..n_insts {
            self.trace_inst(i);
        }

        trace!("")
    }

    fn trace_inst(&self, i: usize) {
        trace!("#{}\t{:30}\t\tdefine: {:?}\tuses: {:?}\tpred: {:?}\tsucc: {:?}",
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        i, demangle_text(self.code[i].code.clone()), self.get_inst_reg_defines(i), self.get_inst_reg_uses(i),
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        self.code[i].preds, self.code[i].succs);
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    }

    fn get_ir_block_livein(&self, block: &str) -> Option<&Vec<MuID>> {
        match self.blocks.get(block) {
            Some(ref block) => Some(&block.livein),
            None => None
        }
    }

    fn get_ir_block_liveout(&self, block: &str) -> Option<&Vec<MuID>> {
        match self.blocks.get(block) {
            Some(ref block) => Some(&block.liveout),
            None => None
        }
    }

    fn set_ir_block_livein(&mut self, block: &str, set: Vec<MuID>) {
        let block = self.blocks.get_mut(block).unwrap();
        block.livein = set;
    }

    fn set_ir_block_liveout(&mut self, block: &str, set: Vec<MuID>) {
        let block = self.blocks.get_mut(block).unwrap();
        block.liveout = set;
    }

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    fn get_all_blocks(&self) -> Vec<MuName> { self.blocks.keys().map(|x| x.clone()).collect() }
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    fn get_entry_block(&self) -> MuName {
        self.entry.clone()
    }

    fn get_block_range(&self, block: &str) -> Option<ops::Range<usize>> {
        match self.blocks.get(block) {
            Some(ref block) => Some(block.start_inst..block.end_inst),
            None => None
        }
    }

    fn get_block_for_inst(&self, index: usize) -> Option<MuName> {
        for (name, block) in self.blocks.iter() {
            if index >= block.start_inst && index < block.end_inst {
                return Some(name.clone());
            }
        }
        None
    }

    fn get_next_inst(&self, index: usize) -> Option<usize> {
        ASMCode::find_next_inst(index, &self.code)
    }

    fn get_last_inst(&self, index: usize) -> Option<usize> {
        ASMCode::find_last_inst(index, &self.code)
    }
}

#[derive(Clone, Debug)]
enum ASMBranchTarget {
    None,
    Conditional(MuName),
    Unconditional(MuName),
    PotentiallyExcepting(MuName),
    Return,
    UnconditionalReg(MuID)
}

#[derive(Clone, Debug)]
enum SpillMemInfo {
    Load(P<Value>),
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    Store(P<Value>),
    CalleeSaved, // Callee saved record
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}

#[derive(Clone, Debug)]
struct ASMInst {
    code: String,

    defines: LinkedHashMap<MuID, Vec<ASMLocation>>,
    uses: LinkedHashMap<MuID, Vec<ASMLocation>>,

    is_mem_op_used: bool,
    is_symbol: bool,

    preds: Vec<usize>,
    succs: Vec<usize>,
    branch: ASMBranchTarget,

    spill_info: Option<SpillMemInfo>
}

impl ASMInst {
    fn symbolic(line: String) -> ASMInst {
        ASMInst {
            code: line,
            defines: LinkedHashMap::new(),
            uses: LinkedHashMap::new(),
            is_mem_op_used: false,
            is_symbol: true,
            preds: vec![],
            succs: vec![],
            branch: ASMBranchTarget::None,

            spill_info: None
        }
    }

    fn inst(
        inst: String,
        defines: LinkedHashMap<MuID, Vec<ASMLocation>>,
        uses: LinkedHashMap<MuID, Vec<ASMLocation>>,
        is_mem_op_used: bool,
        target: ASMBranchTarget,
        spill_info: Option<SpillMemInfo>
    ) -> ASMInst
    {
        ASMInst {
            code: inst,
            defines: defines,
            uses: uses,
            is_symbol: false,
            is_mem_op_used: is_mem_op_used,
            preds: vec![],
            succs: vec![],
            branch: target,

            spill_info: spill_info
        }
    }
}

#[derive(Clone, Debug, PartialEq, Eq)]
struct ASMLocation {
    line: usize,
    index: usize,
    len: usize,
    oplen: usize,
}

impl ASMLocation {
    fn new(line: usize, index: usize, len: usize, oplen: usize) -> ASMLocation {
        ASMLocation{
            line: line,
            index: index,
            len: len,
            oplen: oplen
        }
    }
}

#[derive(Clone, Debug)]
/// [start_inst, end_inst)
struct ASMBlock {
    start_inst: usize,
    end_inst: usize,

    livein: Vec<MuID>,
    liveout: Vec<MuID>
}

impl ASMBlock {
    fn new() -> ASMBlock {
        ASMBlock {
            start_inst: usize::MAX,
            end_inst: usize::MAX,
            livein: vec![],
            liveout: vec![]
        }
    }
}

pub struct ASMCodeGen {
    cur: Option<Box<ASMCode>>
}

const REG_PLACEHOLDER_LEN : usize = 5;
lazy_static! {
    pub static ref REG_PLACEHOLDER : String = {
        let blank_spaces = [' ' as u8; REG_PLACEHOLDER_LEN];

        format!("{}", str::from_utf8(&blank_spaces).unwrap())
    };
}

const FRAME_SIZE_PLACEHOLDER_LEN : usize = 10; // a frame is smaller than 1 << 10
lazy_static! {
    pub static ref FRAME_SIZE_PLACEHOLDER : String = {
        let blank_spaces = [' ' as u8; FRAME_SIZE_PLACEHOLDER_LEN];
        format!("{}", str::from_utf8(&blank_spaces).unwrap())
    };
}

impl ASMCodeGen {
    pub fn new() -> ASMCodeGen {
        ASMCodeGen {
            cur: None
        }
    }

    fn cur(&self) -> &ASMCode {
        self.cur.as_ref().unwrap()
    }

    fn cur_mut(&mut self) -> &mut ASMCode {
        self.cur.as_mut().unwrap()
    }

    fn line(&self) -> usize {
        self.cur().code.len()
    }

    fn add_asm_block_label(&mut self, code: String, block_name: MuName) {
        trace!("emit: [{}]{}", block_name, code);
        self.cur_mut().code.push(ASMInst::symbolic(code));
    }

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    fn add_asm_symbolic(&mut self, code: String) {
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        trace!("emit: {}", code);
        self.cur_mut().code.push(ASMInst::symbolic(code));
    }

    fn add_asm_call(&mut self, code: String, potentially_excepting: Option<MuName>, target: Option<(MuID, ASMLocation)>) {
        // a call instruction will use all the argument registers
        // do not need
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        let mut uses: LinkedHashMap<MuID, Vec<ASMLocation>> = LinkedHashMap::new();
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        if target.is_some() {
            let (id, loc) = target.unwrap();
            uses.insert(id, vec![loc]);
        }
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        //        for reg in ARGUMENT_GPRS.iter() {
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        //            uses.insert(reg.id(), vec![]);
        //        }
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        //        for reg in ARGUMENT_FPRS.iter() {
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        //            uses.insert(reg.id(), vec![]);
        //        }
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        // defines: return registers
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        let mut defines: LinkedHashMap<MuID, Vec<ASMLocation>> = LinkedHashMap::new();
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        for reg in RETURN_GPRS.iter() {
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            defines.insert(reg.id(), vec![]);
        }
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        for reg in RETURN_FPRS.iter() {
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            defines.insert(reg.id(), vec![]);
        }
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        for reg in CALLER_SAVED_GPRS.iter() {
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            if !defines.contains_key(&reg.id()) {
                defines.insert(reg.id(), vec![]);
            }
        }
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        for reg in CALLER_SAVED_FPRS.iter() {
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            if !defines.contains_key(&reg.id()) {
                defines.insert(reg.id(), vec![]);
            }
        }

        self.add_asm_inst_internal(code, defines, uses, false, {
            if potentially_excepting.is_some() {
                ASMBranchTarget::PotentiallyExcepting(potentially_excepting.unwrap())
            } else {
                ASMBranchTarget::None
            }
        }, None)
    }

    fn add_asm_inst(
        &mut self,
        code: String,
        defines: LinkedHashMap<MuID, Vec<ASMLocation>>,
        uses: LinkedHashMap<MuID, Vec<ASMLocation>>,
        is_using_mem_op: bool
    ) {
        self.add_asm_inst_internal(code, defines, uses, is_using_mem_op, ASMBranchTarget::None, None)
    }

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    fn add_asm_inst_with_callee_saved(
        &mut self,
        code: String,
        defines: LinkedHashMap<MuID, Vec<ASMLocation>>,
        uses: LinkedHashMap<MuID, Vec<ASMLocation>>,
        is_using_mem_op: bool,
    ) {
        self.add_asm_inst_internal(code, defines, uses, is_using_mem_op, ASMBranchTarget::None, Some(SpillMemInfo::CalleeSaved))
    }

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    fn add_asm_inst_with_spill(
        &mut self,
        code: String,
        defines: LinkedHashMap<MuID, Vec<ASMLocation>>,
        uses: LinkedHashMap<MuID, Vec<ASMLocation>>,
        is_using_mem_op: bool,
        spill_info: SpillMemInfo
    ) {
        self.add_asm_inst_internal(code, defines, uses, is_using_mem_op, ASMBranchTarget::None, Some(spill_info))
    }

    fn add_asm_inst_internal(
        &mut self,
        code: String,
        defines: LinkedHashMap<MuID, Vec<ASMLocation>>,
        uses: LinkedHashMap<MuID, Vec<ASMLocation>>,
        is_using_mem_op: bool,
        target: ASMBranchTarget,
        spill_info: Option<SpillMemInfo>)
    {
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        trace!("asm: {}", demangle_text(code.clone()));
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        trace!("     defines: {:?}", defines);
        trace!("     uses: {:?}", uses);
        let mc = self.cur_mut();

        // put the instruction
        mc.code.push(ASMInst::inst(code, defines, uses, is_using_mem_op, target, spill_info));
    }

    fn prepare_reg(&self, op: &P<Value>, loc: usize) -> (String, MuID, ASMLocation) {
        if cfg!(debug_assertions) {
            match op.v {
                Value_::SSAVar(_) => {},
                _ => panic!("expecting register op")
            }
        }

        let str = self.asm_reg_op(op);
        let len = str.len();
        (str, op.extract_ssa_id().unwrap(), ASMLocation::new(self.line(), loc, len, check_op_len(&op.ty)))
    }

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    fn prepare_mem(&self, op: &P<Value>, loc: usize) -> (String, LinkedHashMap<MuID, Vec<ASMLocation>>) {
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        if cfg!(debug_assertions) {
            match op.v {
                Value_::Memory(_) => {},
                _ => panic!("expecting memory op")
            }
        }

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        let mut ids: Vec<MuID> = vec![];
        let mut locs: Vec<ASMLocation> = vec![];
        let mut result_str: String = "".to_string();
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        let mut loc_cursor: usize = loc;
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        match op.v {
            // offset(base,index,scale)
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            Value_::Memory(MemoryLocation::Address { ref base, ref offset, shift, signed }) => {
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                result_str.push('[');
                loc_cursor += 1;
                // deal with base, base is ssa
                let (str, id, loc) = self.prepare_reg(base, loc_cursor);
                result_str.push_str(&str);
                ids.push(id);
                locs.push(loc);
                loc_cursor += str.len();

                // deal with offset
                if offset.is_some() {
                    result_str.push(',');
                    loc_cursor += 1;

                    let offset = offset.as_ref().unwrap();
                    match offset.v {
                        Value_::SSAVar(_) => {
                            // temp as offset
                            let (str, id, loc) = self.prepare_reg(offset, loc_cursor);

                            result_str.push_str(&str);
                            ids.push(id);
                            locs.push(loc);

                            result_str.push_str(",");
                            let n = offset.ty.get_int_length().unwrap();
                            let shift_type =
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                                     if n == 64 { if signed { "SXTX" } else { "LSL"  } }
                                else if n == 32 { if signed { "SXTW" } else { "UXTW" } }
                                else            { panic!("Unexpected size for offset register") };
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                            result_str.push_str(&shift_type);
                            result_str.push_str(" #");
                            let shift_str = shift.to_string();
                            result_str.push_str(&shift_str);
                        },
                        Value_::Constant(Constant::Int(val)) => {
                            let str = (val as i32).to_string();

                            result_str.push('#');
                            result_str.push_str(&str);
                        },
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                        Value_::Constant(Constant::ExternSym(ref name)) => {
                            result_str.push('#');
                            result_str.push_str(name.as_str());
                        }
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                        _ => panic!("unexpected offset type: {:?}", offset)
                    }
                }

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                if shift != 0 {}
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                result_str.push(']');
            },

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            Value_::Memory(MemoryLocation::Symbolic { ref label, is_global, is_native }) => {
                let label = if is_native { "/*C*/".to_string() + label.as_str() } else { mangle_name(label.clone()) };
                let label = if is_global { format!(":got:{}", label.clone()) } else { label.clone() };
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                result_str.push_str(label.as_str());
            },
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            Value_::Memory(MemoryLocation::VirtualAddress {..}) => {
                panic!("Can't directly use a virtual adress (try calling emit_mem first)");
            }
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            _ => panic!("expect mem location as value")
        }

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            let mut map: LinkedHashMap<MuID, Vec<ASMLocation>> = linked_hashmap! {};
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            for i in 0..ids.len() {
                let id = ids[i];
                let loc = locs[i].clone();

                if map.contains_key(&id) {
                    map.get_mut(&id).unwrap().push(loc);
                } else {
                    map.insert(id, vec![loc]);
                }
            }
            map
        };


        (result_str, uses)
    }

    fn asm_reg_op(&self, op: &P<Value>) -> String {
        let id = op.extract_ssa_id().unwrap();
        if id < MACHINE_ID_END {
            // machine reg
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        } else {
            // virtual register, use place holder
            REG_PLACEHOLDER.clone()
        }
    }

    fn finish_code_sequence_asm(&mut self) -> Box<ASMCode> {
        self.cur.take().unwrap()
    }

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    fn internal_simple(&mut self, inst: &str) {
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        let inst = inst.to_string();
        trace!("emit: \t{}", inst);

        let asm = inst;

        self.add_asm_inst(
            asm,
            linked_hashmap! {},
            linked_hashmap! {},
            false
        )
    }

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    fn internal_simple_imm(&mut self, inst: &str, val: u64) {
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        let inst = inst.to_string();
        trace!("emit: \t{} {}", inst, val);

        let asm = format!("{} #{}", inst, val);

        self.add_asm_inst(
            asm,
            linked_hashmap! {},
            linked_hashmap! {},
            false
        )
    }

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    fn internal_simple_str(&mut self, inst: &str, option: &str) {
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        let inst = inst.to_string();
        let option = option.to_string();
        trace!("emit: \t{} {}", inst, option);

        let asm = format!("{} {}", inst, option);

        self.add_asm_inst(
            asm,
            linked_hashmap! {},
            linked_hashmap! {},
            false
        )
    }

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    // A system instruction
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    fn internal_system(&mut self, inst: &str, option: &str, src: &P<Value>) {
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        let inst = inst.to_string();
        let option = option.to_string();
        trace!("emit: \t{} {} {}", inst, option, src);

        let (reg1, id1, loc1) = self.prepare_reg(src, inst.len() + 1 + option.len() + 1);

        let asm = format!("{} {},{}", inst, option, reg1);

        self.add_asm_inst(
            asm,
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            linked_hashmap! {},
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            ignore_zero_register(id1, vec![loc1]),
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            false
        )
    }

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    fn internal_branch_op(&mut self, inst: &str, src: &P<Value>, dest_name: MuName) {
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        trace!("emit: \t{} {}, {}", inst, src, dest_name);

        let (reg1, id1, loc1) = self.prepare_reg(src, inst.len() + 1);
        // symbolic label, we dont need to patch it
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        let asm = format!("{} {},{}", inst, reg1, mangle_name(dest_name.clone()));
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        self.add_asm_inst_internal(asm, linked_hashmap! {}, linked_hashmap! { id1 => vec![loc1]}, false, ASMBranchTarget::Conditional(dest_name), None);
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    }

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    fn internal_branch_op_imm(&mut self, inst: &str, src1: &P<Value>, src2: u8, dest_name: MuName) {
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        trace!("emit: \t{} {},{},{}", inst, src1, src2, dest_name);

        let (reg1, id1, loc1) = self.prepare_reg(src1, inst.len() + 1);
        // symbolic label, we dont need to patch it
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        let asm = format!("{} {},#{},{}", inst, reg1, src2, mangle_name(dest_name.clone()));
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        self.add_asm_inst_internal(asm, linked_hashmap! {}, linked_hashmap! { id1 => vec![loc1]}, false, ASMBranchTarget::Conditional(dest_name), None);
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    }

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    // Same as inetnral_binop except extends the second source register
    fn internal_binop_ext(&mut self, inst: &str, dest: &P<Value>, src1: &P<Value>, src2: &P<Value>, signed: bool, shift: u8) {
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        let inst = inst.to_string();
        let ext_s = if signed { "S" } else { "U" };
        let ext_p = match src2.ty.get_int_length() {
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            Some(8) => "B",
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            Some(16) => "H",
            Some(32) => "W",
            Some(64) => "X",
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            _ => panic!("op size: {} dose not support extension", src2.ty.get_int_length().unwrap())
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        };
        let ext = ext_s.to_string() + "XT" + ext_p;

        trace!("emit: \t{} {}, {} {} {} -> {}", inst, src1, src2, ext, shift, dest);


        let (reg1, id1, loc1) = self.prepare_reg(dest, inst.len() + 1);
        let (reg2, id2, loc2) = self.prepare_reg(src1, inst.len() + 1 + reg1.len() + 1);
        let (reg3, id3, loc3) = self.prepare_reg(src2, inst.len() + 1 + reg1.len() + 1 + reg2.len() + 1);

        let asm =
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            if shift == 0 { format!("{} {},{},{},{}", inst, reg1, reg2, reg3, ext) } else { format!("{} {},{},{},{} #{}", inst, reg1, reg2, reg3, ext, shift) };
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        self.add_asm_inst(
            asm,
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            ignore_zero_register(id1, vec![loc1]),
            create_hash_map(vec![(id2, loc2), (id3, loc3)]),
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            false
        )
    }

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    fn internal_binop_imm(&mut self, inst: &str, dest: &P<Value>, src1: &P<Value>, src2: u64, shift: u8) {
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        let inst = inst.to_string();
        trace!("emit: \t{} {}, {} LSL {} -> {}", inst, src1, src2, shift, dest);

        let (reg1, id1, loc1) = self.prepare_reg(dest, inst.len() + 1);
        let (reg2, id2, loc2) = self.prepare_reg(src1, inst.len() + 1 + reg1.len() + 1);

        let asm = if shift == 0 {
            format!("{} {},{},#{}", inst, reg1, reg2, src2)
        } else {
            format!("{} {},{},#{},LSL #{}", inst, reg1, reg2, src2, shift)
        };

        self.add_asm_inst(
            asm,
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            ignore_zero_register(id1, vec![loc1]),
            ignore_zero_register(id2, vec![loc2]),
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            false
        )
    }

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    fn internal_binop_str(&mut self, inst: &str, dest: &P<Value>, src1: &P<Value>, src2: &str) {
        let inst = inst.to_string();
        trace!("emit: \t{} {}, {} -> {}", inst, src1, src2, dest);

        let (reg1, id1, loc1) = self.prepare_reg(dest, inst.len() + 1);
        let (reg2, id2, loc2) = self.prepare_reg(src1, inst.len() + 1 + reg1.len() + 1);

        let asm = format!("{} {},{},#{}", inst, reg1, reg2, src2);

        self.add_asm_inst(
            asm,
            ignore_zero_register(id1, vec![loc1]),
            ignore_zero_register(id2, vec![loc2]),
            false
        )
    }

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    // dest <= inst(src1, src2)
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    fn internal_unop_shift(&mut self, inst: &str, dest: &P<Value>, src: &P<Value>, shift: &str, amount: u8) {
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        let inst = inst.to_string();
        trace!("emit: \t{} {}, {} {} -> {}", inst, src, shift, amount, dest);

        let (reg1, id1, loc1) = self.prepare_reg(dest, inst.len() + 1);
        let (reg2, id2, loc2) = self.prepare_reg(src, inst.len() + 1 + reg1.len() + 1);

        let asm = format!("{} {},{},{} #{}", inst, reg1, reg2, shift, amount);

        self.add_asm_inst(
            asm,
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            ignore_zero_register(id1, vec![loc1]),
            ignore_zero_register(id2, vec![loc2]),
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            false
        )
    }

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    // dest <= inst(src)
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    fn internal_unop(&mut self, inst: &str, dest: &P<Value>, src: &P<Value>) {
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        let inst = inst.to_string();
        trace!("emit: \t{} {} -> {}", inst, src, dest);

        let (reg1, id1, loc1) = self.prepare_reg(dest, inst.len() + 1);
        let (reg2, id2, loc2) = self.prepare_reg(src, inst.len() + 1 + reg1.len() + 1);

        let asm = format!("{} {},{}", inst, reg1, reg2);

        self.add_asm_inst(
            asm,
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            ignore_zero_register(id1, vec![loc1]),
            ignore_zero_register(id2, vec![loc2]),
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            false
        )
    }

    // Note: different instructions have different allowed src values
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    fn internal_unop_imm(&mut self, inst: &str, dest: &P<Value>, src: u64, shift: u8) {
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        debug_assert!(shift == 0 || shift == 16 || shift == 32 || shift == 48);
        let inst = inst.to_string();
        trace!("emit: \t{} {} LSL {} -> {}", inst, src, shift, dest);

        let (reg1, id1, loc1) = self.prepare_reg(dest, inst.len() + 1);
        let asm = if shift == 0 {
            format!("{} {},#{}", inst, reg1, src)
        } else {
            format!("{} {},#{},LSL #{}", inst, reg1, src, shift)
        };

        self.add_asm_inst(
            asm,
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            ignore_zero_register(id1, vec![loc1]),
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            linked_hashmap! {},
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            false
        )
    }


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    // dest <= inst(src1, src2)
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    fn internal_binop(&mut self, inst: &str, dest: &P<Value>, src1: &P<Value>, src2: &P<Value>) {
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        let inst = inst.to_string();
        trace!("emit: \t{} {}, {} -> {}", inst, src1, src2, dest);

        let (reg1, id1, loc1) = self.prepare_reg(dest, inst.len() + 1);
        let (reg2, id2, loc2) = self.prepare_reg(src1, inst.len() + 1 + reg1.len() + 1);
        let (reg3, id3, loc3) = self.prepare_reg(src2, inst.len() + 1 + reg1.len() + 1 + reg2.len() + 1);

        let asm = format!("{} {},{},{}", inst, reg1, reg2, reg3);

        self.add_asm_inst(
            asm,
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            ignore_zero_register(id1, vec![loc1]),
            create_hash_map(vec![(id2, loc2), (id3, loc3)]),
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            false
        )
    }

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    // dest <= inst(src1, src2)
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    fn internal_binop_shift(&mut self, inst: &str, dest: &P<Value>, src1: &P<Value>, src2: &P<Value>, shift: &str, amount: u8) {
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        let inst = inst.to_string();
        trace!("emit: \t{} {}, {}, {} {} -> {}", inst, src1, src2, shift, amount, dest);

        let (reg1, id1, loc1) = self.prepare_reg(dest, inst.len() + 1);
        let (reg2, id2, loc2) = self.prepare_reg(src1, inst.len() + 1 + reg1.len() + 1);
        let (reg3, id3, loc3) = self.prepare_reg(src2, inst.len() + 1 + reg1.len() + 1 + reg2.len() + 1);

        let asm = format!("{} {},{},{},{} #{}", inst, reg1, reg2, reg3, shift, amount);

        self.add_asm_inst(
            asm,
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            ignore_zero_register(id1, vec![loc1]),
            create_hash_map(vec![(id2, loc2), (id3, loc3)]),
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            false
        )
    }

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    // dest <= inst(src1, src2, src3)
    fn internal_ternop(&mut self, inst: &str, dest: &P<Value>, src1: &P<Value>, src2: &P<Value>, src3: &P<Value>) {
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        let inst = inst.to_string();
        trace!("emit: \t{} {}, {}, {} -> {}", inst, src3, src1, src2, dest);

        let (reg1, id1, loc1) = self.prepare_reg(dest, inst.len() + 1);
        let (reg2, id2, loc2) = self.prepare_reg(src1, inst.len() + 1 + reg1.len() + 1);
        let (reg3, id3, loc3) = self.prepare_reg(src2, inst.len() + 1 + reg1.len() + 1 + reg2.len() + 1);
        let (reg4, id4, loc4) = self.prepare_reg(src3, inst.len() + 1 + reg1.len() + 1 + reg2.len() + 1 + reg3.len() + 1);

        let asm = format!("{} {},{},{},{}", inst, reg1, reg2, reg3, reg4);

        self.add_asm_inst(
            asm,
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            ignore_zero_register(id1, vec![loc1]),
            create_hash_map(vec![(id2, loc2), (id3, loc3), (id4, loc4)]),
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            false
        )
    }

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    fn internal_ternop_imm(&mut self, inst: &str, dest: &P<Value>, src1: &P<Value>, src2: u64, src3: u64) {
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        let inst = inst.to_string();
        trace!("emit: \t{} {}, {}, {} -> {}", inst, src1, src2, src3, dest);

        let (reg1, id1, loc1) = self.prepare_reg(dest, inst.len() + 1);
        let (reg2, id2, loc2) = self.prepare_reg(src1, inst.len() + 1 + reg1.len() + 1);

        let asm = format!("{} {},{},#{},#{}", inst, reg1, reg2, src2, src3);

        self.add_asm_inst(
            asm,
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            ignore_zero_register(id1, vec![loc1]),
            ignore_zero_register(id2, vec![loc2]),
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            false
        )
    }

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    // PSTATE.<NZCV> = inst(src1, src2)
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    fn internal_cmpop(&mut self, inst: &str, src1: &P<Value>, src2: &P<Value>)
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    {
        let inst = inst.to_string();
        trace!("emit: \t{} {}, {}", inst, src1, src2);

        let (reg1, id1, loc1) = self.prepare_reg(src1, inst.len() + 1);
        let (reg2, id2, loc2) = self.prepare_reg(src2, inst.len() + 1 + reg1.len() + 1);

        let asm = format!("{} {},{}", inst, reg1, reg2);

        self.add_asm_inst(
            asm,
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            linked_hashmap! {},
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            create_hash_map(vec![(id1, loc1), (id2, loc2)]),
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            false
        )
    }

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    // dest <= inst(src1, src2)
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    fn internal_cmpop_shift(&mut self, inst: &str, src1: &P<Value>, src2: &P<Value>, shift: &str, amount: u8) {
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        let inst = inst.to_string();
        trace!("emit: \t{} {},{}, {} {}", inst, src1, src2, shift, amount);

        let (reg1, id1, loc1) = self.prepare_reg(src1, inst.len() + 1);
        let (reg2, id2, loc2) = self.prepare_reg(src2, inst.len() + 1 + reg1.len() + 1);

        let asm = format!("{} {},{},{} #{}", inst, reg1, reg2, shift, amount);

        self.add_asm_inst(
            asm,
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            linked_hashmap! {},
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            create_hash_map(vec![(id1, loc1), (id2, loc2)]),
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            false
        )
    }

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    // Same as inetnral_binop except extends the second source register
    fn internal_cmpop_ext(&mut self, inst: &str, src1: &P<Value>, src2: &P<Value>, signed: bool, shift: u8) {
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        let inst = inst.to_string();
        let ext_s = if signed { "S" } else { "U" };
        let ext_p = match src2.ty.get_int_length() {
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            Some(8) => "B",
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            Some(16) => "H",
            Some(32) => "W",
            Some(64) => "X",
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            _ => panic!("op size: {} dose not support extension", src2.ty.get_int_length().unwrap())
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        };
        let ext = ext_s.to_string() + "XT" + ext_p;

        trace!("emit: \t{} {}, {} {} {}", inst, src1, src2, ext, shift);


        let (reg1, id1, loc1) = self.prepare_reg(src1, inst.len() + 1);
        let (reg2, id2, loc2) = self.prepare_reg(src2, inst.len() + 1 + reg1.len() + 1);

        let asm = format!("{} {},{},{} #{}", inst, reg1, reg2, ext, shift);

        self.add_asm_inst(
            asm,
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            linked_hashmap! {},
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            create_hash_map(vec![(id1, loc1), (id2, loc2)]),
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            false
        )
    }
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    // PSTATE.<NZCV> = inst(src1, src2 [<< 12])
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    fn internal_cmpop_imm(&mut self, inst: &str, src1: &P<Value>, src2: u64, shift: u8)
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    {
        let inst = inst.to_string();
        trace!("emit: \t{} {}, {} LSL {}", inst, src1, src2, shift);

        let (reg1, id1, loc1) = self.prepare_reg(src1, inst.len() + 1);

        let asm = if shift == 0 {
            format!("{} {},#{}", inst, reg1, src2)
        } else {
            format!("{} {},#{},LSL #{}", inst, reg1, src2, shift)
        };

        self.add_asm_inst(
            asm,
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            linked_hashmap! { },
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            ignore_zero_register(id1, vec![loc1]),
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            false
        )
    }

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    // PSTATE.<NZCV> = inst(src1, 0.0)
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    fn internal_cmpop_f0(&mut self, inst: &str, src1: &P<Value>)
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    {
        let inst = inst.to_string();
        trace!("emit: \t{} {}, 0.0", inst, src1);

        let (reg1, id1, loc1) = self.prepare_reg(src1, inst.len() + 1);

        let asm = format!("{} {},#0.0", inst, reg1);

        self.add_asm_inst(
            asm,
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            linked_hashmap! { },
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            ignore_zero_register(id1, vec![loc1]),
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            false
        )
    }

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    // dest <= inst<cond>()
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    fn internal_cond_op(&mut self, inst: &str, dest: &P<Value>, cond: &str) {
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        let inst = inst.to_string();
        let cond = cond.to_string();
        trace!("emit: \t{} {} -> {}", inst, cond, dest);

        let (reg1, id1, loc1) = self.prepare_reg(dest, inst.len() + 1);

        let asm = format!("{} {},{}", inst, reg1, cond);

        self.add_asm_inst(
            asm,
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            ignore_zero_register(id1, vec![loc1]),
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            linked_hashmap! {},
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            false
        )
    }

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    // dest <= inst<cond>(src)
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    fn internal_cond_unop(&mut self, inst: &str, dest: &P<Value>, src: &P<Value>, cond: &str) {
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        let inst = inst.to_string();
        let cond = cond.to_string();
        trace!("emit: \t{} {} {} -> {}", inst, cond, src, dest);

        let (reg1, id1, loc1) = self.prepare_reg(dest, inst.len() + 1);
        let (reg2, id2, loc2) = self.prepare_reg(src, inst.len() + 1 + reg1.len() + 1);

        let asm = format!("{} {},{},{}", inst, reg1, reg2, cond);

        self.add_asm_inst(
            asm,
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            ignore_zero_register(id1, vec![loc1]),
            ignore_zero_register(id2, vec![loc2]),
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            false
        )
    }

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    // dest <= inst<cond>(src1, src2)
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    fn internal_cond_binop(&mut self, inst: &str, dest: &P<Value>, src1: &P<Value>, src2: &P<Value>, cond: &str) {
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        let inst = inst.to_string();
        let cond = cond.to_string();
        trace!("emit: \t{} {}, {}, {} -> {}", inst, cond, src1, src2, dest);

        let (reg1, id1, loc1) = self.prepare_reg(dest, inst.len() + 1);
        let (reg2, id2, loc2) = self.prepare_reg(src1, inst.len() + 1 + reg1.len() + 1);
        let (reg3, id3, loc3) = self.prepare_reg(src2, inst.len() + 1 + reg1.len() + 1 + reg2.len() + 1);

        let asm = format!("{} {},{},{},{}", inst, reg1, reg2, reg3, cond);

        self.add_asm_inst(
            asm,
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            ignore_zero_register(id1<