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Commit 0236eec6 authored by Isaac Oscar Gariano's avatar Isaac Oscar Gariano
Browse files

Updated name handling on aarch64

parent 2aba65ad
......@@ -756,7 +756,7 @@ impl MachineCode for ASMCode {
fn trace_inst(&self, i: usize) {
trace!("#{}\t{:30}\t\tdefine: {:?}\tuses: {:?}\tpred: {:?}\tsucc: {:?}",
i, demangle_text(self.code[i].code), self.get_inst_reg_defines(i), self.get_inst_reg_uses(i),
i, demangle_text(self.code[i].code.clone()), self.get_inst_reg_defines(i), self.get_inst_reg_uses(i),
self.code[i].preds, self.code[i].succs);
}
......@@ -1062,7 +1062,7 @@ impl ASMCodeGen {
target: ASMBranchTarget,
spill_info: Option<SpillMemInfo>)
{
trace!("asm: {}", demange_text(code));
trace!("asm: {}", demangle_text(code.clone()));
trace!(" defines: {:?}", defines);
trace!(" uses: {:?}", uses);
let mc = self.cur_mut();
......@@ -2014,7 +2014,6 @@ impl CodeGenerator for ASMCodeGen {
fn start_exception_block(&mut self, block_name: MuName) -> ValueLocation {
self.add_asm_symbolic(directive_globl(mangle_name(block_name.clone())));
self.add_asm_symbolic(directive_globl(mangled_name.clone()));
self.start_block(block_name.clone());
......@@ -2684,10 +2683,10 @@ pub fn emit_code(fv: &mut MuFunctionVersion, vm: &VM) {
Ok(file) => file
};
file.write(".arch armv8-a\n".as_bytes()).unwrap();
writeln!(file, ".arch armv8-a").unwrap();
// constants in text section
file.write(".text\n".as_bytes()).unwrap();
writeln!(file, ".text").unwrap();
write_const_min_align(&mut file);
......@@ -2833,7 +2832,7 @@ pub fn emit_context_with_reloc(vm: &VM,
};
// data
file.write(".data\n".as_bytes()).unwrap();
writeln!(file, ".data").unwrap();
{
use runtime::mm;
......@@ -2880,12 +2879,11 @@ pub fn emit_context_with_reloc(vm: &VM,
// .globl global_cell_name
// global_cell_name:
let demangled_name = global_value.name().clone();
let global_cell_name = symbol(mangle_name(demangled_name.clone()));
let global_cell_name = mangle_name(demangled_name.clone());
writeln!(file, "\t{}", directive_globl(global_cell_name.clone())).unwrap();
writeln!(file, "{}:", global_cell_name.clone()).unwrap();
if is_valid_c_identifier(&demangled_name) {
let demangled_name = symbol(demangled_name);
writeln!(file, "\t{}", directive_globl(demangled_name.clone())).unwrap();
writeln!(file, "\t{}", directive_equiv(demangled_name, global_cell_name.clone())).unwrap();
}
......@@ -2893,7 +2891,7 @@ pub fn emit_context_with_reloc(vm: &VM,
// dump_label:
let dump_label = relocatable_refs.get(&obj_dump.reference_addr).unwrap().clone();
writeln!("{}:", dump_label).unwrap();
writeln!(file, "{}:", dump_label).unwrap();
let base = obj_dump.reference_addr;
let end = obj_dump.mem_start.plus(obj_dump.mem_size);
......@@ -2909,7 +2907,7 @@ pub fn emit_context_with_reloc(vm: &VM,
let load_ref = unsafe {cur_addr.load::<Address>()};
if load_ref.is_zero() {
// write 0
file.write(".xword 0\n".as_bytes()).unwrap();
writeln!(file, ".xword 0").unwrap();
} else {
let label = match relocatable_refs.get(&load_ref) {
Some(label) => label,
......
......@@ -295,7 +295,7 @@ impl <'a> InstructionSelection {
self.process_dest(&ops, dest, f_content, f_context, vm);
let target = f_content.get_block(dest.target).name().unwrap();
let target = f_content.get_block(dest.target).name();
trace!("emit branch1");
// jmp
......@@ -319,7 +319,7 @@ impl <'a> InstructionSelection {
// process dest
self.process_dest(&ops, case_dest, f_content, f_context, vm);
let target = f_content.get_block(case_dest.target).name().unwrap();
let target = f_content.get_block(case_dest.target).name();
let mut imm_val = 0 as u64;
// Is one of the arguments a valid immediate?
......@@ -349,7 +349,7 @@ impl <'a> InstructionSelection {
// emit default
self.process_dest(&ops, default, f_content, f_context, vm);
let default_target = f_content.get_block(default.target).name().unwrap();
let default_target = f_content.get_block(default.target).name();
self.backend.emit_b(default_target);
} else {
panic!("expecting cond in switch to be ireg: {}", cond);
......@@ -915,9 +915,9 @@ impl <'a> InstructionSelection {
let res_value = self.get_result_value(node, 0);
let res_success = self.get_result_value(node, 1);
let blk_cmpxchg_start = make_block_name(node, "cmpxchg_start", node.id());
let blk_cmpxchg_failed = make_block_name(node, "cmpxchg_failed", node.id());
let blk_cmpxchg_succeded = make_block_name(node, "cmpxchg_succeded", node.id());
let blk_cmpxchg_start = make_block_name(node, "cmpxchg_start");
let blk_cmpxchg_failed = make_block_name(node, "cmpxchg_failed");
let blk_cmpxchg_succeded = make_block_name(node, "cmpxchg_succeded");
self.finish_block();
......@@ -3484,7 +3484,7 @@ impl <'a> InstructionSelection {
let potentially_excepting = {
if resumption.is_some() {
let target_id = resumption.unwrap().exn_dest.target;
Some(f_content.get_block(target_id).name().unwrap)
Some(f_content.get_block(target_id).name())
} else {
None
}
......@@ -3502,7 +3502,7 @@ impl <'a> InstructionSelection {
unimplemented!()
} else {
let callsite = self.new_callsite_label(Some(cur_node));
self.backend.emit_bl(callsite, target.name().unwrap(), potentially_excepting, false)
self.backend.emit_bl(callsite, target.name(), potentially_excepting, false)
}
} else {
let target = self.emit_ireg(func, f_content, f_context, vm);
......@@ -3559,7 +3559,8 @@ impl <'a> InstructionSelection {
}
fn emit_common_prologue(&mut self, args: &Vec<P<Value>>, sig: &P<CFuncSig>, f_context: &mut FunctionContext, vm: &VM) {
self.start_block(format!("{}:{}", self.current_fv_name, PROLOGUE_BLOCK_NAME), &vec![]);
let prologue_block = format!("{}:{}", self.current_fv_name, PROLOGUE_BLOCK_NAME);
self.start_block(prologue_block, &vec![]);
// Push the frame pointer and link register onto the stack
self.backend.emit_push_pair(&LR, &FP, &SP);
......@@ -3668,7 +3669,8 @@ impl <'a> InstructionSelection {
// Live in are the registers that hold the return values
// (if the value is returned through 'XR' than the caller is responsible for managing lifetime)
let livein = self.compute_return_registers(&ret_type, vm);
self.start_block(format!("{}:{}", self.current_fv_name, EPILOGUE_BLOCK_NAME), &livein);
let epilogue_block = format!("{}:{}", self.current_fv_name, EPILOGUE_BLOCK_NAME);
self.start_block(epilogue_block, &livein);
// pop all callee-saved registers
for i in (0..CALLEE_SAVED_FPRs.len()).rev() {
......@@ -4091,7 +4093,7 @@ impl <'a> InstructionSelection {
// get address from vm
unimplemented!()
} else {
make_value_symbolic(pv.name().unwrap(), true, &pv.ty, vm)
make_value_symbolic(pv.name(), true, &pv.ty, vm)
}
},
Value_::Memory(_) => pv.clone(),
......
......@@ -2178,7 +2178,7 @@ pub fn emit_addr_sym(backend: &mut CodeGenerator, dest: &P<Value>, src: &P<Value
match src.v {
Value_::Memory(ref mem) => {
match mem {
&MemoryLocation::Symbolic{ref label, is_global} => {
&MemoryLocation::Symbolic{ref label, is_global, is_native} => {
if is_global {
// Set dest to be the page address of the entry for src in the GOT
backend.emit_adrp(&dest, &src);
......@@ -2188,7 +2188,12 @@ pub fn emit_addr_sym(backend: &mut CodeGenerator, dest: &P<Value>, src: &P<Value
let offset = P(Value {
hdr: MuEntityHeader::unnamed(vm.next_id()),
ty: UINT64_TYPE.clone(),
v: Value_::Constant(Constant::ExternSym(format!(":got_lo12:{}", label)))
v: Value_::Constant(Constant::ExternSym(
if is_native {
format!("/*C*/:got_lo12:{}", label)
} else {
format!(":got_lo12:{}", mangle_name(label.clone()))
}))
});
// [dest + low 12 bits of the GOT entry for src]
......
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