Commit 30a6d074 authored by qinsoon's avatar qinsoon

reg alloc results for factorial seems reasonable

parent e91f7785
......@@ -14,6 +14,7 @@ use ast::inst::*;
use std::collections::HashMap;
use std::str;
use std::usize;
use std::slice::Iter;
struct ASMCode {
name: MuTag,
......@@ -134,22 +135,6 @@ impl ASM {
uses: vec![]
}
}
fn call(line: String) -> ASM {
ASM {
code: line,
defines: vec![],
uses: vec![]
}
}
fn ret(line: String) -> ASM {
ASM {
code: line,
defines: vec![],
uses: vec![]
}
}
}
#[derive(Clone, Debug)]
......@@ -184,6 +169,8 @@ lazy_static! {
}
impl ASMCodeGen {
pub fn new() -> ASMCodeGen {
ASMCodeGen {
cur: None
......@@ -214,12 +201,25 @@ impl ASMCodeGen {
self.cur_mut().code.push(ASM::symbolic(code));
}
fn prepare_machine_regs(&self, regs: Iter<P<Value>>) -> Vec<MuID> {
regs.map(|x| self.prepare_machine_reg(x)).collect()
}
fn add_asm_call(&mut self, code: String) {
self.cur_mut().code.push(ASM::call(code));
let mut uses : Vec<MuID> = self.prepare_machine_regs(x86_64::ARGUMENT_GPRs.iter());
uses.append(&mut self.prepare_machine_regs(x86_64::ARGUMENT_FPRs.iter()));
let mut defines : Vec<MuID> = self.prepare_machine_regs(x86_64::RETURN_GPRs.iter());
defines.append(&mut self.prepare_machine_regs(x86_64::RETURN_FPRs.iter()));
self.add_asm_inst(code, defines, vec![], uses, vec![]);
}
fn add_asm_ret(&mut self, code: String) {
self.cur_mut().code.push(ASM::ret(code));
let mut uses : Vec<MuID> = self.prepare_machine_regs(x86_64::RETURN_GPRs.iter());
uses.append(&mut self.prepare_machine_regs(x86_64::RETURN_FPRs.iter()));
self.add_asm_inst(code, vec![], vec![], uses, vec![]);
}
fn add_asm_branch(&mut self, code: String, target: &'static str) {
......@@ -516,10 +516,10 @@ impl CodeGenerator for ASMCodeGen {
self.add_asm_inst(
asm,
vec![id1],
vec![loc1],
vec![id2],
vec![loc2]
vec![loc2],
vec![id1],
vec![loc1]
)
}
......@@ -533,8 +533,8 @@ impl CodeGenerator for ASMCodeGen {
self.add_asm_inst(
asm,
vec![id1],
vec![loc1.clone()],
vec![id2],
vec![loc2.clone()],
vec![id1, id2],
vec![loc1, loc2]
)
......@@ -571,8 +571,8 @@ impl CodeGenerator for ASMCodeGen {
self.add_asm_inst(
asm,
vec![id1],
vec![loc1.clone()],
vec![id2],
vec![loc2.clone()],
vec![id1, id2],
vec![loc1, loc2]
)
......@@ -736,10 +736,10 @@ impl CodeGenerator for ASMCodeGen {
self.add_asm_inst(
asm,
vec![id, rsp],
vec![loc],
vec![rsp],
vec![]
vec![],
vec![id, rsp],
vec![loc]
)
}
......
......@@ -81,13 +81,13 @@ lazy_static! {
R15.clone()
];
pub static ref ALL_GPRs : [P<Value>; 16] = [
pub static ref ALL_GPRs : [P<Value>; 15] = [
RAX.clone(),
RCX.clone(),
RDX.clone(),
RBX.clone(),
RSP.clone(),
RBP.clone(),
// RBP.clone(),
RSI.clone(),
RDI.clone(),
R8.clone(),
......@@ -193,6 +193,39 @@ lazy_static! {
XMM14.clone(),
XMM15.clone()
];
pub static ref ALL_USABLE_MACHINE_REGs : Vec<P<Value>> = vec![
RAX.clone(),
RCX.clone(),
RDX.clone(),
RBX.clone(),
RSI.clone(),
RDI.clone(),
R8.clone(),
R9.clone(),
R10.clone(),
R11.clone(),
R12.clone(),
R13.clone(),
R14.clone(),
R15.clone(),
XMM0.clone(),
XMM1.clone(),
XMM2.clone(),
XMM3.clone(),
XMM4.clone(),
XMM5.clone(),
XMM6.clone(),
XMM7.clone(),
XMM8.clone(),
XMM9.clone(),
XMM10.clone(),
XMM11.clone(),
XMM12.clone(),
XMM13.clone(),
XMM14.clone(),
XMM15.clone()
];
}
pub fn init_machine_regs_for_func (func_context: &mut FunctionContext) {
......@@ -228,6 +261,10 @@ pub fn all_regs() -> &'static Vec<P<Value>> {
&ALL_MACHINE_REGs
}
pub fn all_usable_regs() -> &'static Vec<P<Value>> {
&ALL_USABLE_MACHINE_REGs
}
pub fn pick_group_for_reg(reg_id: MuID) -> RegGroup {
match reg_id {
0...15 => RegGroup::GPR,
......
......@@ -18,6 +18,8 @@ pub use compiler::backend::x86_64::number_of_all_regs;
#[cfg(target_arch = "x86_64")]
pub use compiler::backend::x86_64::all_regs;
#[cfg(target_arch = "x86_64")]
pub use compiler::backend::x86_64::all_usable_regs;
#[cfg(target_arch = "x86_64")]
pub use compiler::backend::x86_64::pick_group_for_reg;
#[cfg(target_arch = "arm")]
......
......@@ -87,7 +87,7 @@ impl GraphColoring {
trace!("Initializing coloring allocator...");
// for all machine registers
for reg in backend::all_regs().iter() {
for reg in backend::all_usable_regs().iter() {
let reg_id = reg.extract_ssa_id().unwrap();
let node = self.ig.get_node(reg_id);
......
......@@ -304,12 +304,12 @@ pub fn build (cf: &CompiledFunction, func: &MuFunction) -> InterferenceGraph {
trace!("build live outs");
while !work_list.is_empty() {
let n = work_list.pop_front().unwrap();
// trace!("build liveout for #{}", n);
trace!("build liveout for #{}", n);
let ref mut out_set = live_out[n];
// out = union(in[succ]) for all succs
for succ in cf.mc.get_succs(n) {
// trace!("add successor's livein {:?} to #{}", &live_in[*succ], n);
trace!("add successor's livein {:?} to #{}", &live_in[*succ], n);
vec_utils::add_all(out_set, &live_in[*succ]);
}
......@@ -317,13 +317,14 @@ pub fn build (cf: &CompiledFunction, func: &MuFunction) -> InterferenceGraph {
let mut diff = out_set.clone();
for def in cf.mc.get_inst_reg_defines(n) {
vec_utils::remove_value(&mut diff, *def);
// trace!("removing def: {}", *def);
// trace!("diff = {:?}", diff);
trace!("removing def: {}", *def);
trace!("diff = {:?}", diff);
}
// trace!("out - def = {:?}", diff);
trace!("out - def = {:?}", diff);
if !diff.is_empty() {
let ref mut in_set = live_in[n];
trace!("in = (use) {:?}", in_set);
if vec_utils::add_all(in_set, &diff) {
for p in cf.mc.get_preds(n) {
......@@ -331,7 +332,7 @@ pub fn build (cf: &CompiledFunction, func: &MuFunction) -> InterferenceGraph {
}
}
}
// trace!("in = use + (out - def) = {:?}", live_in[n]);
trace!("in = use + (out - def) = {:?}", live_in[n]);
}
// debug live-outs
......
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