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Commit 48f726b3 authored by qinsoon's avatar qinsoon
Browse files

sext/zext from i1 to i8 is no op

internally int1 is int8
parent 38d18dda
......@@ -8,6 +8,7 @@ use utils::ByteSize;
use compiler::backend::x86_64;
use compiler::backend::x86_64::CodeGenerator;
use compiler::backend::{Reg, Mem};
use compiler::backend::x86_64::check_op_len;
use compiler::machine_code::MachineCode;
use vm::VM;
use runtime::ValueLocation;
......@@ -1463,18 +1464,6 @@ fn op_postfix(op_len: usize) -> &'static str {
}
}
#[inline(always)]
fn check_op_len(op: &P<Value>) -> usize {
match op.ty.get_int_length() {
Some(64) => 64,
Some(32) => 32,
Some(16) => 16,
Some(8) => 8,
Some(1) => 8,
_ => panic!("unimplemented int types: {}", op.ty)
}
}
impl CodeGenerator for ASMCodeGen {
fn start_code(&mut self, func_name: MuName) -> ValueLocation {
self.cur = Some(Box::new(ASMCode {
......
......@@ -827,32 +827,35 @@ impl <'a> InstructionSelection {
}
}
op::ConvOp::ZEXT => {
// currently only use 64bits register
// so set irrelevant bits to 0
let from_ty_len = extract_int_len(from_ty);
let to_ty_len = extract_int_len(to_ty);
let from_ty_size = vm.get_backend_type_info(from_ty.id()).size;
let to_ty_size = vm.get_backend_type_info(to_ty.id()).size;
if self.match_ireg(op) {
let tmp_op = self.emit_ireg(op, f_content, f_context, vm);
let tmp_res = self.get_result_value(node);
if from_ty_size != to_ty_size {
if self.match_ireg(op) {
let tmp_op = self.emit_ireg(op, f_content, f_context, vm);
let tmp_res = self.get_result_value(node);
// movz op -> result
self.backend.emit_movz_r_r(&tmp_res, &tmp_op);
} else {
panic!("unexpected op (expect ireg): {}", op);
// movz op -> result
self.backend.emit_movz_r_r(&tmp_res, &tmp_op);
} else {
panic!("unexpected op (expect ireg): {}", op);
}
}
},
op::ConvOp::SEXT => {
// currently only use 64bits register
// we left shift the value, then arithmetic right shift back
if self.match_ireg(op) {
let tmp_op = self.emit_ireg(op, f_content, f_context, vm);
let tmp_res = self.get_result_value(node);
let from_ty_size = vm.get_backend_type_info(from_ty.id()).size;
let to_ty_size = vm.get_backend_type_info(to_ty.id()).size;
// movs op -> result
self.backend.emit_movs_r_r(&tmp_res, &tmp_op);
} else {
panic!("unexpected op (expect ireg): {}", op)
if from_ty_size != to_ty_size {
if self.match_ireg(op) {
let tmp_op = self.emit_ireg(op, f_content, f_context, vm);
let tmp_res = self.get_result_value(node);
// movs op -> result
self.backend.emit_movs_r_r(&tmp_res, &tmp_op);
} else {
panic!("unexpected op (expect ireg): {}", op)
}
}
}
op::ConvOp::REFCAST | op::ConvOp::PTRCAST => {
......
......@@ -174,6 +174,18 @@ pub fn get_color_for_precolroed(id: MuID) -> MuID {
}
}
#[inline(always)]
pub fn check_op_len(op: &P<Value>) -> usize {
match op.ty.get_int_length() {
Some(64) => 64,
Some(32) => 32,
Some(16) => 16,
Some(8) => 8,
Some(1) => 8,
_ => panic!("unimplemented int types: {}", op.ty)
}
}
lazy_static! {
pub static ref RETURN_GPRs : [P<Value>; 2] = [
RAX.clone(),
......
......@@ -65,6 +65,7 @@ pub fn resolve_backend_type_info (ty: &MuType, vm: &VM) -> BackendTypeInfo {
// integral
MuType_::Int(size_in_bit) => {
match size_in_bit {
1 => BackendTypeInfo{size: 1, alignment: 1, struct_layout: None},
8 => BackendTypeInfo{size: 1, alignment: 1, struct_layout: None},
16 => BackendTypeInfo{size: 2, alignment: 2, struct_layout: None},
32 => BackendTypeInfo{size: 4, alignment: 4, struct_layout: None},
......
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