Fixed bugs with calling and run rustfmt

build.rs

 // Copyright 2017 The Australian National University
-// 
+//
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
 // You may obtain a copy of the License at
-// 
+//
 //     http://www.apache.org/licenses/LICENSE-2.0
-// 
+//
 // Unless required by applicable law or agreed to in writing, software
 // distributed under the License is distributed on an "AS IS" BASIS,
 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@@ -18,10 +18,12 @@ extern crate gcc;
 #[cfg(target_arch = "x86_64")]
 fn main() {
     gcc::compile_library("libruntime_c.a", &["src/runtime/runtime_c_x64_sysv.c"]);
-    
-    gcc::Config::new().flag("-O3").flag("-c")
-                     .file("src/runtime/runtime_asm_x64_sysv.S")
-                     .compile("libruntime_asm.a");
+
+    gcc::Config::new()
+        .flag("-O3")
+        .flag("-c")
+        .file("src/runtime/runtime_asm_x64_sysv.S")
+        .compile("libruntime_asm.a");
 }
 
 #[cfg(target_os = "linux")]
@@ -29,7 +31,9 @@ fn main() {
 fn main() {
     gcc::compile_library("libruntime_c.a", &["src/runtime/runtime_c_aarch64_sysv.c"]);
 
-    gcc::Config::new().flag("-O3").flag("-c")
+    gcc::Config::new()
+        .flag("-O3")
+        .flag("-c")
         .file("src/runtime/runtime_asm_aarch64_sysv.S")
         .compile("libruntime_asm.a");
-}
\ No newline at end of file
+}

src/compiler/backend/arch/aarch64/codegen.rs

 // Copyright 2017 The Australian National University
-// 
+//
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
 // You may obtain a copy of the License at
-// 
+//
 //     http://www.apache.org/licenses/LICENSE-2.0
-// 
+//
 // Unless required by applicable law or agreed to in writing, software
 // distributed under the License is distributed on an "AS IS" BASIS,
 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@@ -21,7 +21,8 @@ use compiler::backend::{Reg, Mem};
 
 pub trait CodeGenerator {
     fn start_code(&mut self, func_name: MuName, entry: MuName) -> ValueLocation;
-    fn finish_code(&mut self, func_name: MuName) -> (Box<MachineCode + Sync + Send>, ValueLocation);
+    fn finish_code(&mut self, func_name: MuName)
+        -> (Box<MachineCode + Sync + Send>, ValueLocation);
 
     // generate unnamed sequence of linear code (no branch)
     fn start_code_sequence(&mut self);
@@ -75,41 +76,64 @@ pub trait CodeGenerator {
 
 
     // loads
-    fn emit_ldr(&mut self, dest: Reg/*GPR or FPR*/, src: Mem, signed: bool); // supports the full full range of addressing modes
+    fn emit_ldr(&mut self, dest: Reg /*GPR or FPR*/, src: Mem, signed: bool); // supports the full full range of addressing modes
     fn emit_ldtr(&mut self, dest: Reg, src: Mem, signed: bool); // [base, #simm9]
-    fn emit_ldur(&mut self, dest: Reg/*GPR or FPR*/, src: Mem, signed: bool); // [base, #simm9]
-    fn emit_ldxr(&mut self, dest: Reg, src: Mem);// [base]
-    fn emit_ldaxr(&mut self, dest: Reg, src: Mem);// [base]
-    fn emit_ldar(&mut self, dest: Reg, src: Mem);// [base]
+    fn emit_ldur(&mut self, dest: Reg /*GPR or FPR*/, src: Mem, signed: bool); // [base, #simm9]
+    fn emit_ldxr(&mut self, dest: Reg, src: Mem); // [base]
+    fn emit_ldaxr(&mut self, dest: Reg, src: Mem); // [base]
+    fn emit_ldar(&mut self, dest: Reg, src: Mem); // [base]
 
-    fn emit_ldp(&mut self, dest1: Reg, dest2: Reg/*GPR or FPR*/, src: Mem); // [base, #simm7], [base], #simm7, [base, #simm7]!
+    fn emit_ldp(&mut self, dest1: Reg, dest2: Reg /*GPR or FPR*/, src: Mem); // [base, #simm7], [base], #simm7, [base, #simm7]!
     fn emit_ldxp(&mut self, dest1: Reg, dest2: Reg, src: Mem); // [base]
     fn emit_ldaxp(&mut self, dest1: Reg, dest2: Reg, src: Mem); // [base]
-    fn emit_ldnp(&mut self, dest1: Reg/*GPR or FPR*/, dest2: Reg/*GPR or FPR*/, src: Mem); // [base, #simm7]
+    fn emit_ldnp(
+        &mut self,
+        dest1: Reg, /*GPR or FPR*/
+        dest2: Reg, /*GPR or FPR*/
+        src: Mem
+    ); // [base, #simm7]
 
     // Stores
-    fn emit_str(&mut self, dest: Mem, src: Reg/*GPR or FPR*/); // supports the full full range of addressing modes
+    fn emit_str(&mut self, dest: Mem, src: Reg /*GPR or FPR*/); // supports the full full range of addressing modes
     fn emit_sttr(&mut self, dest: Mem, src: Reg); // [base, #simm9]
-    fn emit_stur(&mut self, dest: Mem, src: Reg/*GPR or FPR*/); // [base, #simm9]
+    fn emit_stur(&mut self, dest: Mem, src: Reg /*GPR or FPR*/); // [base, #simm9]
     fn emit_stlr(&mut self, dest: Mem, src: Reg); // [base]
     fn emit_stxr(&mut self, dest: Mem, status: Reg, src: Reg); // [base]
     fn emit_stlxr(&mut self, dest: Mem, status: Reg, src: Reg); // [base]
 
-    fn emit_stp(&mut self, dest: Mem, src1: Reg, src2: Reg);  // [base, #simm7], [base], #simm7, [base, #simm7]!
+    fn emit_stp(&mut self, dest: Mem, src1: Reg, src2: Reg); // [base, #simm7], [base], #simm7, [base, #simm7]!
     fn emit_stxp(&mut self, dest: Mem, status: Reg, src1: Reg, src2: Reg); // [base]
     fn emit_stlxp(&mut self, dest: Mem, status: Reg, src1: Reg, src2: Reg); // [base]
-    fn emit_stnp(&mut self, dest: Mem, src1: Reg/*GPR or FPR*/, src2: Reg/*GPR or FPR*/); // [base, #simm7]
+    fn emit_stnp(
+        &mut self,
+        dest: Mem,
+        src1: Reg, /*GPR or FPR*/
+        src2: Reg  /*GPR or FPR*/
+    ); // [base, #simm7]
 
     // Calls
-    fn emit_bl(&mut self, callsite: String, func: MuName, pe: Option<MuName>, args: Vec<P<Value>>, is_native: bool) -> ValueLocation;
-    fn emit_blr(&mut self, callsite: String, func: Reg, pe: Option<MuName>, args: Vec<P<Value>>) -> ValueLocation;
+    fn emit_bl(
+        &mut self,
+        callsite: String,
+        func: MuName,
+        pe: Option<MuName>,
+        args: Vec<P<Value>>,
+        is_native: bool
+    ) -> ValueLocation;
+    fn emit_blr(
+        &mut self,
+        callsite: String,
+        func: Reg,
+        pe: Option<MuName>,
+        args: Vec<P<Value>>
+    ) -> ValueLocation;
 
     // Branches
     fn emit_b(&mut self, dest_name: MuName);
     fn emit_b_func(&mut self, func: MuName, args: Vec<P<Value>>); // For tail calls
     fn emit_b_cond(&mut self, cond: &str, dest_name: MuName);
     fn emit_br(&mut self, dest_address: Reg);
-    fn emit_br_func(&mut self, func_address: Reg, args: Vec<P<Value>>);  // For tail calls
+    fn emit_br_func(&mut self, func_address: Reg, args: Vec<P<Value>>); // For tail calls
 
     fn emit_ret(&mut self, src: Reg);
     fn emit_cbnz(&mut self, src: Reg, dest_name: MuName);
@@ -126,36 +150,36 @@ pub trait CodeGenerator {
     fn emit_adrp(&mut self, dest: Reg, src: Mem);
 
     // Unary ops
-    fn emit_mov(&mut self, dest: Reg/*GPR or SP or ZR*/, src: Reg/*GPR or SP or ZR*/); // The SP and ZR cannot both be used
+    fn emit_mov(&mut self, dest: Reg /*GPR or SP or ZR*/, src: Reg /*GPR or SP or ZR*/); // The SP and ZR cannot both be used
     fn emit_mvn(&mut self, dest: Reg, src: Reg);
     fn emit_neg(&mut self, dest: Reg, src: Reg);
     fn emit_negs(&mut self, dest: Reg, src: Reg);
     fn emit_ngc(&mut self, dest: Reg, src: Reg);
     fn emit_ngcs(&mut self, dest: Reg, src: Reg);
-    fn emit_sxtb(&mut self, dest: Reg/*32*/, src: Reg/*32*/);
-    fn emit_sxth(&mut self, dest: Reg/*32*/, src: Reg/*32*/);
-    fn emit_sxtw(&mut self, dest: Reg/*64*/, src: Reg/*32*/);
-    fn emit_uxtb(&mut self, dest: Reg/*32*/, src: Reg/*32*/);
-    fn emit_uxth(&mut self, dest: Reg/*32*/, src: Reg/*32*/);
+    fn emit_sxtb(&mut self, dest: Reg /*32*/, src: Reg /*32*/);
+    fn emit_sxth(&mut self, dest: Reg /*32*/, src: Reg /*32*/);
+    fn emit_sxtw(&mut self, dest: Reg /*64*/, src: Reg /*32*/);
+    fn emit_uxtb(&mut self, dest: Reg /*32*/, src: Reg /*32*/);
+    fn emit_uxth(&mut self, dest: Reg /*32*/, src: Reg /*32*/);
     fn emit_cls(&mut self, dest: Reg, src: Reg);
     fn emit_clz(&mut self, dest: Reg, src: Reg);
     fn emit_rbit(&mut self, dest: Reg, src: Reg);
     fn emit_rev(&mut self, dest: Reg, src: Reg);
     fn emit_rev16(&mut self, dest: Reg, src: Reg);
-    fn emit_rev32(&mut self, dest: Reg/*64*/, src: Reg);
-    fn emit_rev64(&mut self, dest: Reg/*64*/, src: Reg); // alias of REV
+    fn emit_rev32(&mut self, dest: Reg /*64*/, src: Reg);
+    fn emit_rev64(&mut self, dest: Reg /*64*/, src: Reg); // alias of REV
     fn emit_fabs(&mut self, dest: Reg, src: Reg);
-    fn emit_fcvt(&mut self, dest: Reg, src: Reg/*Must have different size*/);
-    fn emit_fcvtas(&mut self, dest: Reg/*GPR, may have different size*/, src: Reg);
-    fn emit_fcvtau(&mut self, dest: Reg/*GPR, may have different size*/, src: Reg);
-    fn emit_fcvtms(&mut self, dest: Reg/*GPR, may have different size*/, src: Reg);
-    fn emit_fcvtmu(&mut self, dest: Reg/*GPR, may have different size*/, src: Reg);
-    fn emit_fcvtns(&mut self, dest: Reg/*GPR, may have different size*/, src: Reg);
-    fn emit_fcvtnu(&mut self, dest: Reg/*GPR, may have different size*/, src: Reg);
-    fn emit_fcvtps(&mut self, dest: Reg/*GPR, may have different size*/, src: Reg);
-    fn emit_fcvtpu(&mut self, dest: Reg/*GPR, may have different size*/, src: Reg);
-    fn emit_fcvtzs(&mut self, dest: Reg/*GPR, may have different size*/, src: Reg);
-    fn emit_fcvtzu(&mut self, dest: Reg/*GPR, may have different size*/, src: Reg);
+    fn emit_fcvt(&mut self, dest: Reg, src: Reg /*Must have different size*/);
+    fn emit_fcvtas(&mut self, dest: Reg /*GPR, may have different size*/, src: Reg);
+    fn emit_fcvtau(&mut self, dest: Reg /*GPR, may have different size*/, src: Reg);
+    fn emit_fcvtms(&mut self, dest: Reg /*GPR, may have different size*/, src: Reg);
+    fn emit_fcvtmu(&mut self, dest: Reg /*GPR, may have different size*/, src: Reg);
+    fn emit_fcvtns(&mut self, dest: Reg /*GPR, may have different size*/, src: Reg);
+    fn emit_fcvtnu(&mut self, dest: Reg /*GPR, may have different size*/, src: Reg);
+    fn emit_fcvtps(&mut self, dest: Reg /*GPR, may have different size*/, src: Reg);
+    fn emit_fcvtpu(&mut self, dest: Reg /*GPR, may have different size*/, src: Reg);
+    fn emit_fcvtzs(&mut self, dest: Reg /*GPR, may have different size*/, src: Reg);
+    fn emit_fcvtzu(&mut self, dest: Reg /*GPR, may have different size*/, src: Reg);
     fn emit_fmov(&mut self, dest: Reg, src: Reg); // One register must be an FPR, the other may be a GPR or an FPR
     fn emit_fneg(&mut self, dest: Reg, src: Reg);
     fn emit_frinta(&mut self, dest: Reg, src: Reg);
@@ -166,8 +190,8 @@ pub trait CodeGenerator {
     fn emit_frintx(&mut self, dest: Reg, src: Reg);
     fn emit_frintz(&mut self, dest: Reg, src: Reg);
     fn emit_fsqrt(&mut self, dest: Reg, src: Reg);
-    fn emit_scvtf(&mut self, dest: Reg/*FPR, may have different size*/, src: Reg);
-    fn emit_ucvtf(&mut self, dest: Reg/*FPR, may have different size*/, src: Reg);
+    fn emit_scvtf(&mut self, dest: Reg /*FPR, may have different size*/, src: Reg);
+    fn emit_ucvtf(&mut self, dest: Reg /*FPR, may have different size*/, src: Reg);
 
     // Unary operations with shift
     fn emit_mov_shift(&mut self, dest: Reg, src: Reg, shift: &str, ammount: u8);
@@ -184,26 +208,54 @@ pub trait CodeGenerator {
     fn emit_fmov_imm(&mut self, dest: Reg, src: f32);
 
     // Extended binary ops
-    fn emit_add_ext(&mut self, dest: Reg/*GPR or SP*/, src1: Reg/*GPR or SP*/, src2: Reg, signed: bool, shift: u8);
-    fn emit_adds_ext(&mut self, dest: Reg, src1: Reg/*GPR or SP*/, src2: Reg, signed: bool, shift: u8);
-    fn emit_sub_ext(&mut self, dest: Reg/*GPR or SP*/, src1: Reg/*GPR or SP*/, src2: Reg, signed: bool, shift: u8);
-    fn emit_subs_ext(&mut self, dest: Reg, src1: Reg/*GPR or SP*/, src2: Reg, signed: bool, shift: u8);
+    fn emit_add_ext(
+        &mut self,
+        dest: Reg, /*GPR or SP*/
+        src1: Reg, /*GPR or SP*/
+        src2: Reg,
+        signed: bool,
+        shift: u8
+    );
+    fn emit_adds_ext(
+        &mut self,
+        dest: Reg,
+        src1: Reg, /*GPR or SP*/
+        src2: Reg,
+        signed: bool,
+        shift: u8
+    );
+    fn emit_sub_ext(
+        &mut self,
+        dest: Reg, /*GPR or SP*/
+        src1: Reg, /*GPR or SP*/
+        src2: Reg,
+        signed: bool,
+        shift: u8
+    );
+    fn emit_subs_ext(
+        &mut self,
+        dest: Reg,
+        src1: Reg, /*GPR or SP*/
+        src2: Reg,
+        signed: bool,
+        shift: u8
+    );
 
     // Multiplication
     fn emit_mul(&mut self, dest: Reg, src1: Reg, src2: Reg);
     fn emit_mneg(&mut self, dest: Reg, src1: Reg, src2: Reg);
-    fn emit_smulh(&mut self, dest: Reg/*64*/, src1: Reg/*64*/, src2: Reg/*64*/);
-    fn emit_umulh(&mut self, dest: Reg/*64*/, src1: Reg/*64*/, src2: Reg/*64*/);
-    fn emit_smnegl(&mut self, dest: Reg/*64*/, src1: Reg/*32*/, src2: Reg/*32*/);
-    fn emit_smull(&mut self, dest: Reg/*64*/, src1: Reg/*32*/, src2: Reg/*32*/);
-    fn emit_umnegl(&mut self, dest: Reg/*64*/, src1: Reg/*32*/, src2: Reg/*32*/);
-    fn emit_umull(&mut self, dest: Reg/*64*/, src1: Reg/*32*/, src2: Reg/*32*/);
+    fn emit_smulh(&mut self, dest: Reg /*64*/, src1: Reg /*64*/, src2: Reg /*64*/);
+    fn emit_umulh(&mut self, dest: Reg /*64*/, src1: Reg /*64*/, src2: Reg /*64*/);
+    fn emit_smnegl(&mut self, dest: Reg /*64*/, src1: Reg /*32*/, src2: Reg /*32*/);
+    fn emit_smull(&mut self, dest: Reg /*64*/, src1: Reg /*32*/, src2: Reg /*32*/);
+    fn emit_umnegl(&mut self, dest: Reg /*64*/, src1: Reg /*32*/, src2: Reg /*32*/);
+    fn emit_umull(&mut self, dest: Reg /*64*/, src1: Reg /*32*/, src2: Reg /*32*/);
 
     // Other binaries
     fn emit_adc(&mut self, dest: Reg, src1: Reg, src2: Reg);
     fn emit_adcs(&mut self, dest: Reg, src1: Reg, src2: Reg);
-    fn emit_add(&mut self, dest: Reg, src1: Reg/*GPR or SP*/, src2: Reg);
-    fn emit_adds(&mut self, dest: Reg, src1: Reg/*GPR or SP*/, src2: Reg);
+    fn emit_add(&mut self, dest: Reg, src1: Reg /*GPR or SP*/, src2: Reg);
+    fn emit_adds(&mut self, dest: Reg, src1: Reg /*GPR or SP*/, src2: Reg);
     fn emit_sbc(&mut self, dest: Reg, src1: Reg, src2: Reg);
     fn emit_sbcs(&mut self, dest: Reg, src1: Reg, src2: Reg);
     fn emit_sub(&mut self, dest: Reg, src1: Reg, src2: Reg);
@@ -250,15 +302,27 @@ pub trait CodeGenerator {
     fn emit_orr_shift(&mut self, dest: Reg, src1: Reg, src2: Reg, shift: &str, amount: u8);
 
     // binary ops with immediates
-    fn emit_add_imm(&mut self, dest: Reg/*GPR or SP*/, src1: Reg/*GPR or SP*/, src2: u16, shift: bool);
-    fn emit_adds_imm(&mut self, dest: Reg, src1: Reg/*GPR or SP*/, src2: u16, shift: bool);
-    fn emit_sub_imm(&mut self, dest: Reg/*GPR or SP*/, src1: Reg/*GPR or SP*/, src2: u16, shift: bool);
-    fn emit_subs_imm(&mut self, dest: Reg, src1: Reg/*GPR or SP*/, src2: u16, shift: bool);
-
-    fn emit_and_imm(&mut self, dest: Reg/*GPR or SP*/, src1: Reg, src2: u64);
+    fn emit_add_imm(
+        &mut self,
+        dest: Reg, /*GPR or SP*/
+        src1: Reg, /*GPR or SP*/
+        src2: u16,
+        shift: bool
+    );
+    fn emit_adds_imm(&mut self, dest: Reg, src1: Reg /*GPR or SP*/, src2: u16, shift: bool);
+    fn emit_sub_imm(
+        &mut self,
+        dest: Reg, /*GPR or SP*/
+        src1: Reg, /*GPR or SP*/
+        src2: u16,
+        shift: bool
+    );
+    fn emit_subs_imm(&mut self, dest: Reg, src1: Reg /*GPR or SP*/, src2: u16, shift: bool);
+
+    fn emit_and_imm(&mut self, dest: Reg /*GPR or SP*/, src1: Reg, src2: u64);
     fn emit_ands_imm(&mut self, dest: Reg, src1: Reg, src2: u64);
-    fn emit_eor_imm(&mut self, dest: Reg/*GPR or SP*/, src1: Reg, src2: u64);
-    fn emit_orr_imm(&mut self, dest: Reg/*GPR or SP*/, src1: Reg, src2: u64);
+    fn emit_eor_imm(&mut self, dest: Reg /*GPR or SP*/, src1: Reg, src2: u64);
+    fn emit_orr_imm(&mut self, dest: Reg /*GPR or SP*/, src1: Reg, src2: u64);
 
     fn emit_asr_imm(&mut self, dest: Reg, src1: Reg, src2: u8);
     fn emit_lsr_imm(&mut self, dest: Reg, src1: Reg, src2: u8);
@@ -269,10 +333,34 @@ pub trait CodeGenerator {
 
     fn emit_madd(&mut self, dest: Reg, src1: Reg, src2: Reg, src3: Reg);
     fn emit_msub(&mut self, dest: Reg, src1: Reg, src2: Reg, src3: Reg);
-    fn emit_smaddl(&mut self, dest: Reg/*64*/, src1: Reg/*32*/, src2: Reg/*32*/, src3: Reg/*64*/);
-    fn emit_smsubl(&mut self, dest: Reg/*64*/, src1: Reg/*32*/, src2: Reg/*32*/, src3: Reg/*64*/);
-    fn emit_umaddl(&mut self, dest: Reg/*64*/, src1: Reg/*32*/, src2: Reg/*32*/, src3: Reg/*64*/);
-    fn emit_umsubl(&mut self, dest: Reg/*64*/, src1: Reg/*32*/, src2: Reg/*32*/, src3: Reg/*64*/);
+    fn emit_smaddl(
+        &mut self,
+        dest: Reg, /*64*/
+        src1: Reg, /*32*/
+        src2: Reg, /*32*/
+        src3: Reg  /*64*/
+    );
+    fn emit_smsubl(
+        &mut self,
+        dest: Reg, /*64*/
+        src1: Reg, /*32*/
+        src2: Reg, /*32*/
+        src3: Reg  /*64*/
+    );
+    fn emit_umaddl(
+        &mut self,
+        dest: Reg, /*64*/
+        src1: Reg, /*32*/
+        src2: Reg, /*32*/
+        src3: Reg  /*64*/
+    );
+    fn emit_umsubl(
+        &mut self,
+        dest: Reg, /*64*/
+        src1: Reg, /*32*/
+        src2: Reg, /*32*/
+        src3: Reg  /*64*/
+    );
     fn emit_fmadd(&mut self, dest: Reg, src1: Reg, src2: Reg, src3: Reg);
     fn emit_fmsub(&mut self, dest: Reg, src1: Reg, src2: Reg, src3: Reg);
     fn emit_fnmadd(&mut self, dest: Reg, src1: Reg, src2: Reg, src3: Reg);
@@ -297,8 +385,8 @@ pub trait CodeGenerator {
     fn emit_fcmpe(&mut self, src1: Reg, src2: Reg);
 
     // Comparisons with extension
-    fn emit_cmn_ext(&mut self, src1: Reg/*GPR or SP*/, src2: Reg, signed: bool, shift: u8);
-    fn emit_cmp_ext(&mut self, src1: Reg/*GPR or SP*/, src2: Reg, signed: bool, shift: u8);
+    fn emit_cmn_ext(&mut self, src1: Reg /*GPR or SP*/, src2: Reg, signed: bool, shift: u8);
+    fn emit_cmp_ext(&mut self, src1: Reg /*GPR or SP*/, src2: Reg, signed: bool, shift: u8);
 
     // Comparisons with shift
     fn emit_tst_shift(&mut self, src1: Reg, src2: Reg, shift: &str, ammount: u8);
@@ -307,8 +395,8 @@ pub trait CodeGenerator {
 
     // Immediat Comparisons
     fn emit_tst_imm(&mut self, src1: Reg, src2: u64);
-    fn emit_cmn_imm(&mut self, src1: Reg/*GPR or SP*/, src2: u16, shift : bool);
-    fn emit_cmp_imm(&mut self, src1: Reg/*GPR or SP*/, src2: u16, shift : bool);
+    fn emit_cmn_imm(&mut self, src1: Reg /*GPR or SP*/, src2: u16, shift: bool);
+    fn emit_cmp_imm(&mut self, src1: Reg /*GPR or SP*/, src2: u16, shift: bool);
 
     // Comparison against 0
     fn emit_fcmp_0(&mut self, src: Reg);

src/compiler/backend/arch/x86_64/mod.rs

@@ -47,7 +47,7 @@ use utils::LinkedHashMap;
 use std::collections::HashMap;
 
 // number of normal callee saved registers (excluding RSP and RBP)
-pub const CALLEE_SAVED_COUNT : usize = 5;
+pub const CALLEE_SAVED_COUNT: usize = 5;
 
 /// a macro to declare a set of general purpose registers that are aliased to the first one
 macro_rules! GPR_ALIAS {
@@ -250,8 +250,8 @@ pub fn check_op_len(op: &P<Value>) -> usize {
         Some(64) => 64,
         Some(32) => 32,
         Some(16) => 16,
-        Some(8)  => 8,
-        Some(1)  => 8,
+        Some(8) => 8,
+        Some(1) => 8,
         _ => panic!("unsupported register length for x64: {}", op.ty)
     }
 }
@@ -320,7 +320,7 @@ lazy_static! {
     ];
 }
 
-pub const FPR_ID_START : usize = 100;
+pub const FPR_ID_START: usize = 100;
 
 lazy_static!{
     // floating point registers, we use SSE registers
@@ -496,7 +496,7 @@ lazy_static! {
 }
 
 /// creates context for each machine register in FunctionContext
-pub fn init_machine_regs_for_func (func_context: &mut FunctionContext) {
+pub fn init_machine_regs_for_func(func_context: &mut FunctionContext) {
     for reg in ALL_MACHINE_REGS.values() {
         let reg_id = reg.extract_ssa_id().unwrap();
         let entry = SSAVarEntry::new(reg.clone());
@@ -508,9 +508,9 @@ pub fn init_machine_regs_for_func (func_context: &mut FunctionContext) {
 /// gets the number of registers in a certain register group
 pub fn number_of_usable_regs_in_group(group: RegGroup) -> usize {
     match group {
-        RegGroup::GPR   => ALL_USABLE_GPRS.len(),
+        RegGroup::GPR => ALL_USABLE_GPRS.len(),
         RegGroup::GPREX => ALL_USABLE_GPRS.len(),
-        RegGroup::FPR   => ALL_USABLE_FPRS.len()
+        RegGroup::FPR => ALL_USABLE_FPRS.len()
     }
 }
 
@@ -574,9 +574,9 @@ pub fn get_callee_saved_offset(reg: MuID) -> isize {
     let id = if reg == RBX.id() {
         0
     } else {
-        (reg - R12.id())/4 + 1
+        (reg - R12.id()) / 4 + 1
     };
-    (id as isize + 1)*(-8)
+    (id as isize + 1) * (-8)
 }
 
 /// is a machine register (by ID) callee saved?
@@ -597,9 +597,8 @@ pub fn is_valid_x86_imm(op: &P<Value>) -> bool {
 
     if op.ty.get_int_length().is_some() && op.ty.get_int_length().unwrap() <= 32 {
         match op.v {
-            Value_::Constant(Constant::Int(val)) if val as i32 >= i32::MIN && val as i32 <= i32::MAX => {
-                true
-            },
+            Value_::Constant(Constant::Int(val))
+                if val as i32 >= i32::MIN && val as i32 <= i32::MAX => true,
             _ => false
         }
     } else {
@@ -615,49 +614,53 @@ pub fn estimate_insts_for_ir(inst: &Instruction) -> usize {
 
     match inst.v {
         // simple
-        BinOp(_, _, _)  => 1,
+        BinOp(_, _, _) => 1,
         BinOpWithStatus(_, _, _, _) => 2,
-        CmpOp(_, _, _)  => 1,
-        ConvOp{..}      => 0,
+        CmpOp(_, _, _) => 1,
+        ConvOp { .. } => 0,
 
         // control flow
-        Branch1(_)     => 1,
-        Branch2{..}    => 1,
-        Select{..}     => 2,
-        Watchpoint{..} => 1,
-        WPBranch{..}   => 2,
-        Switch{..}     => 3,
+        Branch1(_) => 1,
+        Branch2 { .. } => 1,
+        Select { .. } => 2,
+        Watchpoint { .. } => 1,
+        WPBranch { .. } => 2,
+        Switch { .. } => 3,
 
         // call
-        ExprCall{..} | ExprCCall{..} | Call{..} | CCall{..} => 5,
-        Return(_)   => 1,
+        ExprCall { .. } | ExprCCall { .. } | Call { .. } | CCall { .. } => 5,
+        Return(_) => 1,
         TailCall(_) => 1,
 
         // memory access
-        Load{..} | Store{..} => 1,
-        CmpXchg{..}          => 1,
-        AtomicRMW{..}        => 1,
-        AllocA(_)            => 1,
-        AllocAHybrid(_, _)   => 1,
-        Fence(_)             => 1,
+        Load { .. } | Store { .. } => 1,
+        CmpXchg { .. } => 1,
+        AtomicRMW { .. } => 1,
+        AllocA(_) => 1,
+        AllocAHybrid(_, _) => 1,
+        Fence(_) => 1,
 
         // memory addressing
-        GetIRef(_) | GetFieldIRef{..} | GetElementIRef{..} | ShiftIRef{..} | GetVarPartIRef{..} => 0,
+        GetIRef(_) |
+        GetFieldIRef { .. } |
+        GetElementIRef { .. } |
+        ShiftIRef { .. } |
+        GetVarPartIRef { .. } => 0,
 
         // runtime call
         New(_) | NewHybrid(_, _) => 10,
         NewStack(_) | NewThread(_, _) | NewThreadExn(_, _) | NewFrameCursor(_) => 10,
-        ThreadExit    => 10,
-        Throw(_)      => 10,
-        SwapStack{..} => 10,
+        ThreadExit => 10,
+        Throw(_) => 10,
+        SwapStack { .. } => 10,
         CommonInst_GetThreadLocal | CommonInst_SetThreadLocal(_) => 10,
         CommonInst_Pin(_) | CommonInst_Unpin(_) => 10,
 
         // others
         Move(_) => 0,
-        PrintHex(_)  => 10,
+        PrintHex(_) => 10,
         SetRetval(_) => 10,
-        ExnInstruction{ref inner, ..} => estimate_insts_for_ir(&inner),
-        _ => unimplemented!(),
+        ExnInstruction { ref inner, .. } => estimate_insts_for_ir(&inner),
+        _ => unimplemented!()
     }
 }

src/compiler/backend/inst_sel.rs

 // Copyright 2017 The Australian National University
-// 
+//
 // Licensed under the Apache License, Version 2.0 (the "License");
 // you may not use this file except in compliance with the License.
 // You may obtain a copy of the License at
-// 
+//
 //     http://www.apache.org/licenses/LICENSE-2.0
-// 
+//
 // Unless required by applicable law or agreed to in writing, software
 // distributed under the License is distributed on an "AS IS" BASIS,
 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.