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Commit 4ca214f6 authored by root's avatar root
Browse files

Fixed compilation error for the x86_64 backend

parent 81a87444
......@@ -1701,6 +1701,7 @@ fn emit_reg_value(backend: &mut CodeGenerator, pv: &P<Value>, f_context: &mut Fu
tmp
//}
},
&Constant::IntEx(ref val) => { unimplemented!() },
&Constant::FuncRef(func_id) => {
let tmp = make_temporary(f_context, pv.ty.clone(), vm);
......@@ -1750,6 +1751,7 @@ pub fn emit_ireg_value(backend: &mut CodeGenerator, pv: &P<Value>, f_context: &m
tmp
//}
},
&Constant::IntEx(ref val) => { unimplemented!() },
&Constant::FuncRef(_) => {
unimplemented!();
},
......
......@@ -1910,8 +1910,11 @@ impl <'a> InstructionSelection {
}
}
128 => {
let reg_op1 = self.emit_ireg(&op1, f_content, f_context, vm);
let reg_op2 = self.emit_ireg(&op2, f_content, f_context, vm);
self.emit_runtime_entry(&entrypoints::UDIV_U128,
vec![op1.clone(), op2.clone()],
vec![reg_op1, reg_op2],
Some(vec![res_tmp.clone()]),
Some(node), f_content, f_context, vm);
}
......@@ -1941,8 +1944,11 @@ impl <'a> InstructionSelection {
}
}
128 => {
let reg_op1 = self.emit_ireg(&op1, f_content, f_context, vm);
let reg_op2 = self.emit_ireg(&op2, f_content, f_context, vm);
self.emit_runtime_entry(&entrypoints::SDIV_I128,
vec![op1.clone(), op2.clone()],
vec![reg_op1, reg_op2],
Some(vec![res_tmp.clone()]),
Some(node), f_content, f_context, vm);
}
......@@ -1972,10 +1978,14 @@ impl <'a> InstructionSelection {
}
}
128 => {
let reg_op1 = self.emit_ireg(&op1, f_content, f_context, vm);
let reg_op2 = self.emit_ireg(&op2, f_content, f_context, vm);
self.emit_runtime_entry(&entrypoints::UREM_U128,
vec![op1.clone(), op2.clone()],
vec![reg_op1, reg_op2],
Some(vec![res_tmp.clone()]),
Some(node), f_content, f_context, vm);
}
_ => unimplemented!()
}
......@@ -2003,8 +2013,11 @@ impl <'a> InstructionSelection {
}
}
128 => {
let reg_op1 = self.emit_ireg(&op1, f_content, f_context, vm);
let reg_op2 = self.emit_ireg(&op2, f_content, f_context, vm);
self.emit_runtime_entry(&entrypoints::SREM_I128,
vec![op1.clone(), op2.clone()],
vec![reg_op1, reg_op2],
Some(vec![res_tmp.clone()]),
Some(node), f_content, f_context, vm);
}
......@@ -3840,6 +3853,7 @@ impl <'a> InstructionSelection {
self.backend.emit_mov_r64_imm64(&tmp, val as i64);
}
},
&Constant::IntEx(ref vals) => { unimplemented!() },
&Constant::FuncRef(func_id) => {
if cfg!(target_os = "macos") {
let mem = self.get_mem_for_funcref(func_id, vm);
......
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