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Commit 6456325b authored by Isaac Oscar Gariano's avatar Isaac Oscar Gariano
Browse files

More bug fixes and formating fixes

parent 2c08ff8c
......@@ -21,7 +21,7 @@ export MU_LOG_LEVEL=none
export RUST_TEST_THREADS=1
export RUST_BACKTRACE=0
export PYTHONPATH="$MU_ZEBU/tests/test_jit/mu-client-pypy/:$MU_ZEBU/tests/test_jit/RPySOM/src"
export LD_LIBRARY_PATH="$MU_ZEBU/tests/test_jit/:$MU_ZEBU/tests/test_jit"
export LD_LIBRARY_PATH="$MU_ZEBU/tests/test_jit/:$MU_ZEBU/tests/test_jit:$LD_LIBRARY_PATH"
export ZEBU_BUILD=release
rm -rf $MU_ZEBU/emit
......@@ -29,7 +29,7 @@ rm -rf $MU_ZEBU/tests/test_jit/emit
cargo update
#cargo clean
cargo-fmt -- --write-mode=diff --verbose -- src/ast/src/lib.rs src/gc/src/lib.rs src/utils/src/lib.rs | tee cargo_fmt_out.txt
cargo-fmt -- --write-mode=diff --verbose -- src/lib.rs src/ast/src/lib.rs src/gc/src/lib.rs src/utils/src/lib.rs | tee cargo_fmt_out.txt
cargo test --release --no-run --color=always 2>&1 | tee build_out.txt
$(exit ${PIPESTATUS[0]}) # this command will exit the shell but only if the above cargo test failed
......
......@@ -530,7 +530,6 @@ impl ASMCode {
fn add_frame_size_upper_patchpoint(&mut self, patchpoint: ASMLocation) {
self.frame_size_upper_patchpoints.push(patchpoint);
}
}
use std::any::Any;
......@@ -1224,7 +1223,7 @@ impl ASMCodeGen {
let shift_type = if n == 64 {
if signed {
"LSL"
//"SXTX"
//"SXTX"
} else {
"LSL"
}
......@@ -2375,7 +2374,12 @@ impl CodeGenerator for ASMCodeGen {
let asm = format!("SUB SP,SP,#{}", FRAME_SIZE_PART_PLACEHOLDER.clone());
let line = self.line();
self.cur_mut()
.add_frame_size_lower_patchpoint(ASMLocation::new(line, 11, FRAME_SIZE_PART_PLACEHOLDER_LEN, 0));
.add_frame_size_lower_patchpoint(ASMLocation::new(
line,
11,
FRAME_SIZE_PART_PLACEHOLDER_LEN,
0
));
self.add_asm_inst(
asm,
......@@ -2387,7 +2391,12 @@ impl CodeGenerator for ASMCodeGen {
let asm = format!("SUB SP,SP,#{},LSL #12", FRAME_SIZE_PART_PLACEHOLDER.clone());
let line = self.line();
self.cur_mut()
.add_frame_size_upper_patchpoint(ASMLocation::new(line, 11, FRAME_SIZE_PART_PLACEHOLDER_LEN, 0));
.add_frame_size_upper_patchpoint(ASMLocation::new(
line,
11,
FRAME_SIZE_PART_PLACEHOLDER_LEN,
0
));
self.add_asm_inst(
asm,
......
......@@ -4833,6 +4833,14 @@ impl<'a> InstructionSelection {
self.record_callsite(resumption, callsite, stack_arg_size);
if resumption.is_some() {
self.finish_block();
// This is needed as the above call instruction may 'branch' to the exceptional
// destination, branches are only supposed to occur at the end of assembly blocks
let block_name = make_block_name(&cur_node.name(), "normal_cont_for_call");
self.start_block(block_name);
}
// deal with ret vals
self.emit_postcall_convention(
&func_sig.ret_tys,
......@@ -4843,6 +4851,12 @@ impl<'a> InstructionSelection {
f_context,
vm
);
if resumption.is_some() {
let ref normal_dest = resumption.as_ref().unwrap().normal_dest;
let normal_target_name = f_content.get_block(normal_dest.target).name();
self.backend.emit_b(normal_target_name);
}
}
}
......
......@@ -2749,7 +2749,8 @@ fn emit_move_value_to_value(
Value_::Constant(Constant::FuncRef(id)) => id,
_ => unreachable!()
};
let mem = make_value_symbolic(vm.get_name_for_func(func_id), true, &ADDRESS_TYPE, vm);
let mem =
make_value_symbolic(vm.get_name_for_func(func_id), true, &ADDRESS_TYPE, vm);
emit_calculate_address(backend, &dest, &mem, vm);
} else if is_int_reg(&src) {
backend.emit_mov(dest, src);
......
......@@ -1402,7 +1402,7 @@ impl<'lb, 'lvm> BundleLoader<'lb, 'lvm> {
let sty = P(MuType::new(id, MuType_::muref(t.clone())));
self.built_types.insert(id, sty.clone());
sty
},
}
_ => ty.clone()
};
......
......@@ -54,4 +54,4 @@ mod deps {
extern crate mu_ast as ast;
}
pub use self::api_impl::VALIDATE_IR;
\ No newline at end of file
pub use self::api_impl::VALIDATE_IR;
......@@ -235,7 +235,7 @@ def build_quicksort_bundle(bldr, rmu):
j = bldr.gen_sym("@partition.v1.blk3.j")
i = bldr.gen_sym("@partition.v1.blk3.i")
parr = bldr.gen_sym("@partition.v1.blk3.parr")
pelm = bldr.gen_sym("@partition.v1.blk2.pelm")
pelm = bldr.gen_sym("@partition.v1.blk3.pelm")
pelm_i = bldr.gen_sym("@partition.v1.blk3.pelm_i")
t = bldr.gen_sym("@partition.v1.blk3.t")
pelm_j = bldr.gen_sym("@partition.v1.blk3.pelm_j")
......@@ -258,7 +258,7 @@ def build_quicksort_bundle(bldr, rmu):
i = bldr.gen_sym("@partition.v1.blk4.i")
parr = bldr.gen_sym("@partition.v1.blk4.parr")
idx_high = bldr.gen_sym("@partition.v1.blk4.idx_high")
pelm = bldr.gen_sym("@partition.v1.blk2.pelm")
pelm = bldr.gen_sym("@partition.v1.blk4.pelm")
pelm_i = bldr.gen_sym("@partition.v1.blk4.pelm_i")
t = bldr.gen_sym("@partition.v1.blk4.t")
pelm_idx_high = bldr.gen_sym("@partition.v1.blk4.pelm_idx_high")
......
......@@ -213,3 +213,31 @@ def test_xor():
RET r
}
""", "test_xor");
def test_exc_pass_values():
compile_bundle(
"""
.funcsig sig = (ref<void> int<64>)->(int<32>)
.funcdef test_exc_pass_values <main_sig>
{
entry(<int<32>>argc <uptr<uptr<char>>>argv):
BRANCH blk2(<int<64>>4 <ref<void>>NULL)
blk2(<int<64>> v82555 <ref<void>> container_13):
index_2893 = CALL <sig> excy(container_13 v82555) EXC(blk3(index_2893) blk4(v82555 container_13))
blk3(<int<32>> v82556):
RET v82556
blk4(<int<64>> name_231 <ref<void>> container_14):
a_32 = TRUNC <int<64> int<32>> name_231
RET a_32
}
.funcdef excy <sig>
{
entry(<ref<void>>a0 <int<64>>a5):
THROW <ref<void>>NULL
}
""", "test_exc_pass_values");
assert(execute("test_exc_pass_values") == 4);
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