[wip] refactor: remove is_int_reg()/is_fp_reg() from Value, always check

with RegGroup::get_from_value

src/ast/src/ir.rs

@@ -702,16 +702,17 @@ impl Value {
             _ => false
         }
     }
-    
-    pub fn is_int_reg(&self) -> bool {
+
+    pub fn is_reg(&self) -> bool {
         match self.v {
-            Value_::SSAVar(_) => {
-                if is_scalar(&self.ty) && !is_fp(&self.ty) {
-                    true
-                } else {
-                    false
-                }
-            }
+            Value_::SSAVar(_) => true,
+            _ => false
+        }
+    }
+
+    pub fn is_const(&self) -> bool {
+        match self.v {
+            Value_::Constant(_) => true,
             _ => false
         }
     }
@@ -724,21 +725,6 @@ impl Value {
         })
     }
 
-    pub fn is_fp_reg(&self) -> bool {
-        match self.v {
-            Value_::SSAVar(_) => {
-                if is_scalar(&self.ty) && is_fp(&self.ty) {
-                    true
-                } else {
-                    false
-                }
-            },
-            Value_::Constant(Constant::Double(_)) => true,
-            Value_::Constant(Constant::Float(_))  => true,
-            _ => false
-        }
-    }
-
     pub fn is_int_const(&self) -> bool {
         match self.v {
             Value_::Constant(Constant::Int(_)) => true,

src/compiler/backend/arch/x86_64/mod.rs

@@ -425,8 +425,9 @@ pub fn init_machine_regs_for_func (func_context: &mut FunctionContext) {
 
 pub fn number_of_regs_in_group(group: RegGroup) -> usize {
     match group {
-        RegGroup::GPR => ALL_GPRs.len(),
-        RegGroup::FPR => ALL_FPRs.len()
+        RegGroup::GPR   => ALL_GPRs.len(),
+        RegGroup::GPREX => ALL_GPRs.len(),
+        RegGroup::FPR   => ALL_FPRs.len()
     }
 }
 
@@ -444,13 +445,7 @@ pub fn all_usable_regs() -> &'static Vec<P<Value>> {
 
 pub fn pick_group_for_reg(reg_id: MuID) -> RegGroup {
     let reg = all_regs().get(&reg_id).unwrap();
-    if reg.is_int_reg() {
-        RegGroup::GPR
-    } else if reg.is_fp_reg() {
-        RegGroup::FPR
-    } else {
-        panic!("expect a machine reg to be either a GPR or a FPR: {}", reg)
-    }
+    RegGroup::get_from_value(reg)
 }
 
 pub fn is_callee_saved(reg_id: MuID) -> bool {

src/compiler/backend/mod.rs

@@ -315,10 +315,10 @@ impl fmt::Display for BackendTypeInfo {
 }
 
 #[derive(Clone, Copy, Debug, PartialEq, Eq, Hash, RustcEncodable, RustcDecodable)]
-pub enum RegGroup {GPR, FPR}
+pub enum RegGroup {GPR, GPREX, FPR}
 
 impl RegGroup {
-    pub fn get(ty: &P<MuType>) -> RegGroup {
+    pub fn get_from_ty(ty: &P<MuType>) -> RegGroup {
         match ty.v {
             // for now, only use 64bits registers
             MuType_::Int(len) if len == 1  => RegGroup::GPR,
@@ -326,6 +326,7 @@ impl RegGroup {
             MuType_::Int(len) if len == 16 => RegGroup::GPR,
             MuType_::Int(len) if len == 32 => RegGroup::GPR,
             MuType_::Int(len) if len == 64 => RegGroup::GPR,
+            MuType_::Int(len) if len == 128=> RegGroup::GPREX,
 
             MuType_::Ref(_)
             | MuType_::IRef(_)
@@ -343,4 +344,8 @@ impl RegGroup {
             _ => unimplemented!()
         }
     }
+
+    pub fn get_from_value(val: &P<Value>) -> RegGroup {
+        RegGroup::get_from_ty(&val.ty)
+    }
 }

src/compiler/backend/reg_alloc/graph_coloring/liveness.rs

@@ -43,7 +43,7 @@ impl InterferenceGraph {
             let node = GraphNode {
                 temp: reg_id,
                 color: None,
-                group: backend::RegGroup::get(entry.ty()),
+                group: backend::RegGroup::get_from_ty(entry.ty()),
                 spill_cost: 0.0f32
             };
 

src/runtime/thread.rs

@@ -120,6 +120,7 @@ impl MuStack {
             
             match reg_group {
                 RegGroup::GPR => gpr_used.push(word),
+                RegGroup::GPREX => unimplemented!(),
                 RegGroup::FPR => fpr_used.push(word),
             }
         }