Commit fa95a9b4 authored by qinsoon's avatar qinsoon

add pattern for const operands

parent 42e7c338
...@@ -1608,8 +1608,8 @@ impl ASMCodeGen { ...@@ -1608,8 +1608,8 @@ impl ASMCodeGen {
self.cur.take().unwrap() self.cur.take().unwrap()
} }
/// emits an instruction (use 1 reg, define none) /// emits an instruction (use 0 reg, define 1)
fn internal_uniop_def_r(&mut self, inst: &str, op: &P<Value>) { fn internal_uniop_def_nouse_r(&mut self, inst: &str, op: &P<Value>) {
trace!("emit: {} {}", inst, op); trace!("emit: {} {}", inst, op);
let (reg, id, loc) = self.prepare_reg(op, inst.len() + 1); let (reg, id, loc) = self.prepare_reg(op, inst.len() + 1);
...@@ -1626,6 +1626,26 @@ impl ASMCodeGen { ...@@ -1626,6 +1626,26 @@ impl ASMCodeGen {
) )
} }
/// emits an instruction (use 1 reg, define 1 reg)
fn internal_uniop_def_r(&mut self, inst: &str, op: &P<Value>) {
trace!("emit: {} {}", inst, op);
let (reg, id, loc) = self.prepare_reg(op, inst.len() + 1);
let asm = format!("{} {}", inst, reg);
self.add_asm_inst(
asm,
linked_hashmap!{
id => vec![loc.clone()]
},
linked_hashmap!{
id => vec![loc]
},
false
)
}
/// emits an instruction (use 2 regs, define none) /// emits an instruction (use 2 regs, define none)
fn internal_binop_no_def_r_r(&mut self, inst: &str, op1: &P<Value>, op2: &P<Value>) { fn internal_binop_no_def_r_r(&mut self, inst: &str, op1: &P<Value>, op2: &P<Value>) {
let len = check_op_len(op1); let len = check_op_len(op1);
...@@ -2608,46 +2628,46 @@ impl CodeGenerator for ASMCodeGen { ...@@ -2608,46 +2628,46 @@ impl CodeGenerator for ASMCodeGen {
// set byte // set byte
fn emit_sets_r8(&mut self, dest: Reg) { fn emit_sets_r8(&mut self, dest: Reg) {
self.internal_uniop_def_r("sets", dest) self.internal_uniop_def_nouse_r("sets", dest)
} }
fn emit_setz_r8(&mut self, dest: Reg) { fn emit_setz_r8(&mut self, dest: Reg) {
self.internal_uniop_def_r("setz", dest) self.internal_uniop_def_nouse_r("setz", dest)
} }
fn emit_seto_r8(&mut self, dest: Reg) { fn emit_seto_r8(&mut self, dest: Reg) {
self.internal_uniop_def_r("seto", dest) self.internal_uniop_def_nouse_r("seto", dest)
} }
fn emit_setb_r8(&mut self, dest: Reg) { fn emit_setb_r8(&mut self, dest: Reg) {
self.internal_uniop_def_r("setb", dest) self.internal_uniop_def_nouse_r("setb", dest)
} }
fn emit_seta_r(&mut self, dest: Reg) { fn emit_seta_r(&mut self, dest: Reg) {
self.internal_uniop_def_r("seta", dest) self.internal_uniop_def_nouse_r("seta", dest)
} }
fn emit_setae_r(&mut self, dest: Reg) { fn emit_setae_r(&mut self, dest: Reg) {
self.internal_uniop_def_r("setae", dest) self.internal_uniop_def_nouse_r("setae", dest)
} }
fn emit_setb_r(&mut self, dest: Reg) { fn emit_setb_r(&mut self, dest: Reg) {
self.internal_uniop_def_r("setb", dest) self.internal_uniop_def_nouse_r("setb", dest)
} }
fn emit_setbe_r(&mut self, dest: Reg) { fn emit_setbe_r(&mut self, dest: Reg) {
self.internal_uniop_def_r("setbe", dest) self.internal_uniop_def_nouse_r("setbe", dest)
} }
fn emit_sete_r(&mut self, dest: Reg) { fn emit_sete_r(&mut self, dest: Reg) {
self.internal_uniop_def_r("sete", dest) self.internal_uniop_def_nouse_r("sete", dest)
} }
fn emit_setg_r(&mut self, dest: Reg) { fn emit_setg_r(&mut self, dest: Reg) {
self.internal_uniop_def_r("setg", dest) self.internal_uniop_def_nouse_r("setg", dest)
} }
fn emit_setge_r(&mut self, dest: Reg) { fn emit_setge_r(&mut self, dest: Reg) {
self.internal_uniop_def_r("setge", dest) self.internal_uniop_def_nouse_r("setge", dest)
} }
fn emit_setl_r(&mut self, dest: Reg) { fn emit_setl_r(&mut self, dest: Reg) {
self.internal_uniop_def_r("setl", dest) self.internal_uniop_def_nouse_r("setl", dest)
} }
fn emit_setle_r(&mut self, dest: Reg) { fn emit_setle_r(&mut self, dest: Reg) {
self.internal_uniop_def_r("setle", dest) self.internal_uniop_def_nouse_r("setle", dest)
} }
fn emit_setne_r(&mut self, dest: Reg) { fn emit_setne_r(&mut self, dest: Reg) {
self.internal_uniop_def_r("setne", dest) self.internal_uniop_def_nouse_r("setne", dest)
} }
// cmov src -> dest // cmov src -> dest
...@@ -2824,6 +2844,20 @@ impl CodeGenerator for ASMCodeGen { ...@@ -2824,6 +2844,20 @@ impl CodeGenerator for ASMCodeGen {
self.internal_binop_def_r_imm("sbb", dest, src) self.internal_binop_def_r_imm("sbb", dest, src)
} }
// inc and dec
fn emit_inc_r(&mut self, dest: Reg) {
self.internal_uniop_def_r("inc", dest)
}
fn emit_inc_mem(&mut self, dest: Mem) {
unimplemented!()
}
fn emit_dec_r(&mut self, dest: Reg) {
self.internal_uniop_def_r("dec", dest)
}
fn emit_dec_mem(&mut self, dest: Mem) {
unimplemented!()
}
fn emit_mul_r(&mut self, src: &P<Value>) { fn emit_mul_r(&mut self, src: &P<Value>) {
let len = check_op_len(src); let len = check_op_len(src);
...@@ -3526,6 +3560,14 @@ impl CodeGenerator for ASMCodeGen { ...@@ -3526,6 +3560,14 @@ impl CodeGenerator for ASMCodeGen {
self.internal_fp_binop_no_def_r_r("ucomiss", op1, op2); self.internal_fp_binop_no_def_r_r("ucomiss", op1, op2);
} }
// bitwise - float
fn emit_xorps_f32_f32(&mut self, dest: Reg, src: Reg) {
self.internal_fp_binop_def_r_r("xorps", &dest, &src)
}
fn emit_xorpd_f64_f64(&mut self, dest: Reg, src: Reg) {
self.internal_fp_binop_def_r_r("xorpd", &dest, &src)
}
// add - double // add - double
fn emit_addsd_f64_f64(&mut self, dest: &P<Value>, src: &P<Value>) { fn emit_addsd_f64_f64(&mut self, dest: &P<Value>, src: &P<Value>) {
......
...@@ -178,6 +178,12 @@ pub trait CodeGenerator { ...@@ -178,6 +178,12 @@ pub trait CodeGenerator {
fn emit_sbb_r_mem(&mut self, dest: Reg, src: Mem); fn emit_sbb_r_mem(&mut self, dest: Reg, src: Mem);
fn emit_sbb_r_imm(&mut self, dest: Reg, src: i32); fn emit_sbb_r_imm(&mut self, dest: Reg, src: i32);
// inc and dec
fn emit_inc_r(&mut self, dest: Reg);
fn emit_inc_mem(&mut self, dest: Mem);
fn emit_dec_r(&mut self, dest: Reg);
fn emit_dec_mem(&mut self, dest: Mem);
// multiply // multiply
fn emit_mul_r(&mut self, src: Reg); fn emit_mul_r(&mut self, src: Reg);
fn emit_mul_mem(&mut self, src: Mem); fn emit_mul_mem(&mut self, src: Mem);
...@@ -320,6 +326,10 @@ pub trait CodeGenerator { ...@@ -320,6 +326,10 @@ pub trait CodeGenerator {
fn emit_comiss_f32_f32(&mut self, op1: Reg, op2: Reg); fn emit_comiss_f32_f32(&mut self, op1: Reg, op2: Reg);
fn emit_ucomiss_f32_f32(&mut self, op1: Reg, op2: Reg); fn emit_ucomiss_f32_f32(&mut self, op1: Reg, op2: Reg);
// fp bitwise
fn emit_xorps_f32_f32(&mut self, dest: Reg, src: Reg);
fn emit_xorpd_f64_f64(&mut self, dest: Reg, src: Reg);
// fp conversion // fp conversion
fn emit_cvtsi2sd_f64_r(&mut self, dest: Reg, src: Reg); fn emit_cvtsi2sd_f64_r(&mut self, dest: Reg, src: Reg);
fn emit_cvtsd2si_r_f64(&mut self, dest: Reg, src: Reg); fn emit_cvtsd2si_r_f64(&mut self, dest: Reg, src: Reg);
...@@ -332,7 +342,6 @@ pub trait CodeGenerator { ...@@ -332,7 +342,6 @@ pub trait CodeGenerator {
fn emit_cvtss2sd_f64_f32(&mut self, dest: Reg, src: Reg); fn emit_cvtss2sd_f64_f32(&mut self, dest: Reg, src: Reg);
// used for unsigned int to fp conversion // used for unsigned int to fp conversion
fn emit_cvttsd2si_r_f64(&mut self, dest: Reg, src: Reg); fn emit_cvttsd2si_r_f64(&mut self, dest: Reg, src: Reg);
fn emit_cvttss2si_r_f32(&mut self, dest: Reg, src: Reg); fn emit_cvttss2si_r_f32(&mut self, dest: Reg, src: Reg);
......
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