1. 07 Jan, 2017 1 commit
  2. 05 Dec, 2016 1 commit
  3. 04 Dec, 2016 2 commits
  4. 29 Nov, 2016 1 commit
  5. 24 Nov, 2016 3 commits
    • qinsoon's avatar
      fixed a few problems · 751795b1
      qinsoon authored
      1. asm call do not use all argument registers (otherwise it will keep
      them alive)
      2. spilling a register that is used and defined in one instruction will
      result in creating one new temporary, instead of two
      3. spilling now deals with floating point
      4. SELECT with int8 is implemented using conditional jump (cmov cannot
      take reg8)
      5. postcall convention now deals correctly with fp return values
      6. reg alloc conservative() was wrong in a few commits ago, fixed it
      7. in liveness analysis, when finding a move between a temp and a
      register, find the color for the register (such as RAX for EAX)
      751795b1
    • qinsoon's avatar
      fmul, fadd, frem, sitofp, fptosi · 8aa0b809
      qinsoon authored
      8aa0b809
    • qinsoon's avatar
      floating point jit-test · 3cee78aa
      qinsoon authored
      3cee78aa
  6. 23 Nov, 2016 2 commits
    • qinsoon's avatar
      fp add with two constants · 443d866a
      qinsoon authored
      currently mov constant as imm to a GPR, then mov from GPR
      to xmm. A better approach should be put the immediate in memroy,
      and load it
      443d866a
    • qinsoon's avatar
      fix test_extern_func · 62870f1f
      qinsoon authored
      when we add interefence between %a and %edi, we also add %a with %rdi
      because we cannot assign rdi to a
      62870f1f
  7. 22 Nov, 2016 1 commit
  8. 18 Nov, 2016 1 commit
    • qinsoon's avatar
      add VMOptions · f79120b2
      qinsoon authored
      1. see vm/vm_options.rs for usage and default values
      2. added mu_fastimpl_new_with_opts under vm/api/api_impl/muvm.rs
      f79120b2
  9. 17 Nov, 2016 1 commit
  10. 16 Nov, 2016 2 commits
  11. 15 Nov, 2016 2 commits
    • qinsoon's avatar
      sext/zext from i1 to i8 is no op · 48f726b3
      qinsoon authored
      internally int1 is int8
      48f726b3
    • qinsoon's avatar
      start using 8/16/32 bits registers · 38d18dda
      qinsoon authored
      1. compiler knows all the registers
      2. but only 64bits register is a color (for reg alloc)
      3. backend records the length of GPR for each operand during instruction
      selection
      4. after reg alloc, when replacing temp with a color, find corresponding
      GPR for the length recorded before
      38d18dda
  12. 14 Nov, 2016 2 commits
  13. 11 Nov, 2016 1 commit
  14. 10 Nov, 2016 1 commit
  15. 08 Nov, 2016 1 commit
  16. 04 Nov, 2016 1 commit
    • qinsoon's avatar
      fib in test-jit runs · 5b723a45
      qinsoon authored
      1. grow/shrink frame size in the pro/epilogue. Note: though we removed
      push/pop for unused callee saved registers, we still reserve frame space
      for them. Because we generate spill on frame before we know exactly how
      large a space is. The solution is to make spill locations patchable.
      2. control flow will combine branches in switch instruction if they all
      target the same destination.
      5b723a45
  17. 03 Nov, 2016 3 commits
  18. 02 Nov, 2016 2 commits
  19. 01 Nov, 2016 2 commits
  20. 31 Oct, 2016 3 commits
  21. 28 Oct, 2016 2 commits
  22. 27 Oct, 2016 1 commit
  23. 26 Oct, 2016 1 commit
  24. 25 Oct, 2016 2 commits
  25. 19 Oct, 2016 1 commit