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introduced Move instruction at IR level.
Intermediate blocks will be inserted for multi-target branch
instructions

internally int1 is int8

1. compiler knows all the registers
2. but only 64bits register is a color (for reg alloc)
3. backend records the length of GPR for each operand during instruction
selection
4. after reg alloc, when replacing temp with a color, find corresponding
GPR for the length recorded before

currently we only use 64bit registers, extend/truncate result if it is
not 64bits. This is awful. Going to use all the registers, for example,
AL, AX, EAX, RAX, but will not use AH (so reg alloc is simpler)

Note: made two places in api implementation as unimplemented as
the instruction/type chnaged.

1. grow/shrink frame size in the pro/epilogue. Note: though we removed
push/pop for unused callee saved registers, we still reserve frame space
for them. Because we generate spill on frame before we know exactly how
large a space is. The solution is to make spill locations patchable.
2. control flow will combine branches in switch instruction if they all
target the same destination.

shl, shr, xor, and. Need to deal with large constant which cannot be fit
as instruction immediate (32bits)

now)

now

(throw, new not working)