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  1. 01 Feb, 2017 1 commit
  2. 31 Jan, 2017 1 commit
  3. 20 Jan, 2017 1 commit
  4. 19 Jan, 2017 1 commit
  5. 18 Jan, 2017 1 commit
  6. 17 Jan, 2017 2 commits
  7. 16 Jan, 2017 1 commit
  8. 12 Jan, 2017 1 commit
  9. 11 Jan, 2017 1 commit
  10. 10 Jan, 2017 1 commit
  11. 05 Jan, 2017 1 commit
  12. 25 Nov, 2016 1 commit
  13. 24 Nov, 2016 3 commits
    • qinsoon's avatar
      fixed a few problems · 751795b1
      qinsoon authored
      1. asm call do not use all argument registers (otherwise it will keep
      them alive)
      2. spilling a register that is used and defined in one instruction will
      result in creating one new temporary, instead of two
      3. spilling now deals with floating point
      4. SELECT with int8 is implemented using conditional jump (cmov cannot
      take reg8)
      5. postcall convention now deals correctly with fp return values
      6. reg alloc conservative() was wrong in a few commits ago, fixed it
      7. in liveness analysis, when finding a move between a temp and a
      register, find the color for the register (such as RAX for EAX)
      751795b1
    • qinsoon's avatar
      fmul, fadd, frem, sitofp, fptosi · 8aa0b809
      qinsoon authored
      8aa0b809
    • qinsoon's avatar
      floating point jit-test · 3cee78aa
      qinsoon authored
      3cee78aa
  14. 23 Nov, 2016 1 commit
    • qinsoon's avatar
      fp add with two constants · 443d866a
      qinsoon authored
      currently mov constant as imm to a GPR, then mov from GPR
      to xmm. A better approach should be put the immediate in memroy,
      and load it
      443d866a
  15. 17 Nov, 2016 2 commits
  16. 16 Nov, 2016 3 commits
  17. 15 Nov, 2016 2 commits
    • qinsoon's avatar
      sext/zext from i1 to i8 is no op · 48f726b3
      qinsoon authored
      internally int1 is int8
      48f726b3
    • qinsoon's avatar
      start using 8/16/32 bits registers · 38d18dda
      qinsoon authored
      1. compiler knows all the registers
      2. but only 64bits register is a color (for reg alloc)
      3. backend records the length of GPR for each operand during instruction
      selection
      4. after reg alloc, when replacing temp with a color, find corresponding
      GPR for the length recorded before
      38d18dda
  18. 14 Nov, 2016 2 commits
  19. 11 Nov, 2016 4 commits
  20. 10 Nov, 2016 1 commit
  21. 09 Nov, 2016 1 commit
  22. 08 Nov, 2016 1 commit
  23. 07 Nov, 2016 2 commits
  24. 04 Nov, 2016 2 commits
    • qinsoon's avatar
      fib in test-jit runs · 5b723a45
      qinsoon authored
      1. grow/shrink frame size in the pro/epilogue. Note: though we removed
      push/pop for unused callee saved registers, we still reserve frame space
      for them. Because we generate spill on frame before we know exactly how
      large a space is. The solution is to make spill locations patchable.
      2. control flow will combine branches in switch instruction if they all
      target the same destination.
      5b723a45
    • qinsoon's avatar
      implement switch · a5af3d18
      qinsoon authored
      a5af3d18
  25. 03 Nov, 2016 3 commits