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  1. 12 Jul, 2017 2 commits
  2. 10 Jul, 2017 2 commits
  3. 09 Jul, 2017 2 commits
  4. 08 Jul, 2017 1 commit
  5. 30 Jun, 2017 1 commit
  6. 29 Jun, 2017 1 commit
  7. 28 Jun, 2017 1 commit
  8. 27 Jun, 2017 1 commit
  9. 22 Jun, 2017 1 commit
  10. 16 Jun, 2017 2 commits
  11. 02 Jun, 2017 1 commit
  12. 31 May, 2017 1 commit
  13. 11 May, 2017 1 commit
  14. 08 May, 2017 1 commit
  15. 03 May, 2017 3 commits
  16. 19 Apr, 2017 1 commit
  17. 03 Apr, 2017 1 commit
  18. 03 Feb, 2017 1 commit
  19. 11 Jan, 2017 1 commit
  20. 10 Jan, 2017 3 commits
  21. 07 Jan, 2017 1 commit
  22. 20 Dec, 2016 1 commit
  23. 30 Nov, 2016 1 commit
  24. 23 Nov, 2016 2 commits
  25. 18 Nov, 2016 1 commit
    • qinsoon's avatar
      add VMOptions · f79120b2
      qinsoon authored
      1. see vm/vm_options.rs for usage and default values
      2. added mu_fastimpl_new_with_opts under vm/api/api_impl/muvm.rs
      f79120b2
  26. 15 Nov, 2016 2 commits
    • qinsoon's avatar
      sext/zext from i1 to i8 is no op · 48f726b3
      qinsoon authored
      internally int1 is int8
      48f726b3
    • qinsoon's avatar
      start using 8/16/32 bits registers · 38d18dda
      qinsoon authored
      1. compiler knows all the registers
      2. but only 64bits register is a color (for reg alloc)
      3. backend records the length of GPR for each operand during instruction
      selection
      4. after reg alloc, when replacing temp with a color, find corresponding
      GPR for the length recorded before
      38d18dda
  27. 14 Nov, 2016 2 commits
  28. 09 Nov, 2016 1 commit
  29. 02 Nov, 2016 1 commit