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  1. 16 Nov, 2016 3 commits
  2. 15 Nov, 2016 2 commits
    • qinsoon's avatar
      sext/zext from i1 to i8 is no op · 48f726b3
      qinsoon authored
      internally int1 is int8
      48f726b3
    • qinsoon's avatar
      start using 8/16/32 bits registers · 38d18dda
      qinsoon authored
      1. compiler knows all the registers
      2. but only 64bits register is a color (for reg alloc)
      3. backend records the length of GPR for each operand during instruction
      selection
      4. after reg alloc, when replacing temp with a color, find corresponding
      GPR for the length recorded before
      38d18dda
  3. 14 Nov, 2016 2 commits
  4. 11 Nov, 2016 4 commits
  5. 10 Nov, 2016 1 commit
  6. 09 Nov, 2016 1 commit
  7. 08 Nov, 2016 1 commit
  8. 07 Nov, 2016 2 commits
  9. 04 Nov, 2016 2 commits
    • qinsoon's avatar
      fib in test-jit runs · 5b723a45
      qinsoon authored
      1. grow/shrink frame size in the pro/epilogue. Note: though we removed
      push/pop for unused callee saved registers, we still reserve frame space
      for them. Because we generate spill on frame before we know exactly how
      large a space is. The solution is to make spill locations patchable.
      2. control flow will combine branches in switch instruction if they all
      target the same destination.
      5b723a45
    • qinsoon's avatar
      implement switch · a5af3d18
      qinsoon authored
      a5af3d18
  10. 03 Nov, 2016 3 commits
  11. 02 Nov, 2016 1 commit
  12. 01 Nov, 2016 1 commit
  13. 31 Oct, 2016 3 commits
  14. 28 Oct, 2016 4 commits
  15. 26 Oct, 2016 1 commit
  16. 25 Oct, 2016 1 commit
    • qinsoon's avatar
      reg alloc works fine · db9e7d2f
      qinsoon authored
      (for callee saved regs, we insert push/pop before reg alloc. and
      after allocation, remove unnecessary ones)
      db9e7d2f
  17. 20 Oct, 2016 1 commit
  18. 14 Oct, 2016 1 commit
  19. 11 Oct, 2016 2 commits
  20. 10 Oct, 2016 2 commits
  21. 05 Oct, 2016 1 commit
  22. 30 Sep, 2016 1 commit