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  1. 22 Nov, 2016 1 commit
  2. 18 Nov, 2016 1 commit
    • qinsoon's avatar
      add VMOptions · f79120b2
      qinsoon authored
      1. see vm/vm_options.rs for usage and default values
      2. added mu_fastimpl_new_with_opts under vm/api/api_impl/muvm.rs
      f79120b2
  3. 17 Nov, 2016 1 commit
  4. 16 Nov, 2016 2 commits
  5. 15 Nov, 2016 2 commits
    • qinsoon's avatar
      sext/zext from i1 to i8 is no op · 48f726b3
      qinsoon authored
      internally int1 is int8
      48f726b3
    • qinsoon's avatar
      start using 8/16/32 bits registers · 38d18dda
      qinsoon authored
      1. compiler knows all the registers
      2. but only 64bits register is a color (for reg alloc)
      3. backend records the length of GPR for each operand during instruction
      selection
      4. after reg alloc, when replacing temp with a color, find corresponding
      GPR for the length recorded before
      38d18dda
  6. 14 Nov, 2016 2 commits
  7. 11 Nov, 2016 1 commit
  8. 10 Nov, 2016 1 commit
  9. 08 Nov, 2016 1 commit
  10. 04 Nov, 2016 1 commit
    • qinsoon's avatar
      fib in test-jit runs · 5b723a45
      qinsoon authored
      1. grow/shrink frame size in the pro/epilogue. Note: though we removed
      push/pop for unused callee saved registers, we still reserve frame space
      for them. Because we generate spill on frame before we know exactly how
      large a space is. The solution is to make spill locations patchable.
      2. control flow will combine branches in switch instruction if they all
      target the same destination.
      5b723a45
  11. 03 Nov, 2016 3 commits
  12. 02 Nov, 2016 2 commits
  13. 01 Nov, 2016 2 commits
  14. 31 Oct, 2016 3 commits
  15. 28 Oct, 2016 2 commits
  16. 27 Oct, 2016 1 commit
  17. 26 Oct, 2016 1 commit
  18. 25 Oct, 2016 2 commits
  19. 19 Oct, 2016 2 commits
  20. 17 Oct, 2016 3 commits
  21. 14 Oct, 2016 3 commits
  22. 10 Oct, 2016 1 commit
  23. 05 Oct, 2016 1 commit
  24. 04 Oct, 2016 1 commit