Commit 69f7c5de authored by qinsoon's avatar qinsoon

add a few patterns for cmp regarding mem

parent 4ad58f47
Pipeline #1222 passed with stages
in 54 minutes and 3 seconds
......@@ -2523,6 +2523,10 @@ impl CodeGenerator for ASMCodeGen {
self.internal_binop_no_def_mem_r("cmp", op1, op2)
}
fn emit_cmp_r_mem(&mut self, op1: &P<Value>, op2: &P<Value>) {
self.internal_binop_no_def_r_mem("cmp", op1, op2)
}
fn emit_test_r_r(&mut self, op1: &P<Value>, op2: &P<Value>) {
self.internal_binop_no_def_r_r("test", op1, op2)
}
......
......@@ -61,7 +61,8 @@ pub trait CodeGenerator {
// comparison
fn emit_cmp_r_r(&mut self, op1: Reg, op2: Reg);
fn emit_cmp_imm_r(&mut self, op1: i32, op2: Reg);
fn emit_cmp_mem_r(&mut self, op1: Reg, op2: Reg);
fn emit_cmp_mem_r(&mut self, op1: Mem, op2: Reg);
fn emit_cmp_r_mem(&mut self, op1: Reg, op2: Mem);
fn emit_test_r_r(&mut self, op1: Reg, op2: Reg);
fn emit_test_imm_r(&mut self, op1: i32, op2: Reg);
......
......@@ -5107,6 +5107,20 @@ impl<'a> InstructionSelection {
self.backend.emit_cmp_imm_r(iimm_op2, &reg_op1);
return op;
} else if self.match_ireg(op1) && self.match_mem(op2) {
let reg_op1 = self.emit_ireg(op1, f_content, f_context, vm);
let mem_op2 = self.emit_mem(op2, f_context, vm);
self.backend.emit_cmp_mem_r(&mem_op2, &reg_op1);
return op;
} else if self.match_mem(op1) && self.match_ireg(op2) {
let mem_op1 = self.emit_mem(op1, f_context, vm);
let reg_op2 = self.emit_ireg(op2, f_content, f_context, vm);
self.backend.emit_cmp_r_mem(&mem_op1, &reg_op2);
return op;
} else if self.match_ireg(op1) && self.match_ireg(op2) {
// comparing two iregs (general case)
......
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