Commit 89c1f1cb authored by qinsoon's avatar qinsoon

reformat code byy rustfmt

parent d1df3753
Pipeline #749 failed with stages
in 3 minutes and 12 seconds
// Copyright 2017 The Australian National University
//
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
//
// http://www.apache.org/licenses/LICENSE-2.0
//
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
......@@ -18,10 +18,12 @@ extern crate gcc;
#[cfg(target_arch = "x86_64")]
fn main() {
gcc::compile_library("libruntime_c.a", &["src/runtime/runtime_c_x64_sysv.c"]);
gcc::Config::new().flag("-O3").flag("-c")
.file("src/runtime/runtime_asm_x64_sysv.S")
.compile("libruntime_asm.a");
gcc::Config::new()
.flag("-O3")
.flag("-c")
.file("src/runtime/runtime_asm_x64_sysv.S")
.compile("libruntime_asm.a");
}
#[cfg(target_os = "linux")]
......@@ -29,7 +31,9 @@ fn main() {
fn main() {
gcc::compile_library("libruntime_c.a", &["src/runtime/runtime_c_aarch64_sysv.c"]);
gcc::Config::new().flag("-O3").flag("-c")
gcc::Config::new()
.flag("-O3")
.flag("-c")
.file("src/runtime/runtime_asm_aarch64_sysv.S")
.compile("libruntime_asm.a");
}
\ No newline at end of file
}
......@@ -26,13 +26,13 @@ use std::fmt;
pub struct Instruction {
pub hdr: MuEntityHeader,
/// the values this instruction holds
pub value : Option<Vec<P<Value>>>,
pub value: Option<Vec<P<Value>>>,
/// ops field list all the children nodes,
/// and in Instruction_, the children nodes are referred by indices
/// This design makes it easy for the compiler to iterate through all the children
pub ops : Vec<P<TreeNode>>,
pub ops: Vec<P<TreeNode>>,
/// used for pattern matching
pub v: Instruction_
pub v: Instruction_,
}
// Instruction implements MuEntity
......@@ -44,7 +44,7 @@ impl Clone for Instruction {
hdr: self.hdr.clone(),
value: self.value.clone(),
ops: self.ops.clone(),
v: self.v.clone()
v: self.v.clone(),
}
}
}
......@@ -63,62 +63,62 @@ impl Instruction {
use inst::Instruction_::*;
match self.v {
BinOp(_, _, _)
| BinOpWithStatus(_, _, _, _)
| CmpOp(_, _, _)
| ConvOp{..}
| ExprCall{..}
| ExprCCall{..}
| Load{..}
| Store{..}
| CmpXchg{..}
| AtomicRMW{..}
| New(_)
| AllocA(_)
| NewHybrid(_, _)
| AllocAHybrid(_, _)
| NewStack(_)
| NewThread(_, _)
| NewThreadExn(_, _)
| NewFrameCursor(_)
| GetIRef(_)
| GetFieldIRef{..}
| GetElementIRef{..}
| ShiftIRef{..}
| GetVarPartIRef{..}
| Select{..}
| Fence(_)
| CommonInst_GetThreadLocal
| CommonInst_SetThreadLocal(_)
| CommonInst_Pin(_)
| CommonInst_Unpin(_)
| CommonInst_GetAddr(_)
| CommonInst_Tr64IsFp(_)
| CommonInst_Tr64IsInt(_)
| CommonInst_Tr64IsRef(_)
| CommonInst_Tr64FromFp(_)
| CommonInst_Tr64FromInt(_)
| CommonInst_Tr64FromRef(_, _)
| CommonInst_Tr64ToFp(_)
| CommonInst_Tr64ToInt(_)
| CommonInst_Tr64ToRef(_)
| CommonInst_Tr64ToTag(_)
| Move(_)
| PrintHex(_)
| SetRetval(_) => false,
Return(_)
| ThreadExit
| Throw(_)
| TailCall(_)
| Branch1(_)
| Branch2{..}
| Watchpoint{..}
| WPBranch{..}
| Call{..}
| CCall{..}
| SwapStack{..}
| Switch{..}
| ExnInstruction{..} => true
BinOp(_, _, _) |
BinOpWithStatus(_, _, _, _) |
CmpOp(_, _, _) |
ConvOp { .. } |
ExprCall { .. } |
ExprCCall { .. } |
Load { .. } |
Store { .. } |
CmpXchg { .. } |
AtomicRMW { .. } |
New(_) |
AllocA(_) |
NewHybrid(_, _) |
AllocAHybrid(_, _) |
NewStack(_) |
NewThread(_, _) |
NewThreadExn(_, _) |
NewFrameCursor(_) |
GetIRef(_) |
GetFieldIRef { .. } |
GetElementIRef { .. } |
ShiftIRef { .. } |
GetVarPartIRef { .. } |
Select { .. } |
Fence(_) |
CommonInst_GetThreadLocal |
CommonInst_SetThreadLocal(_) |
CommonInst_Pin(_) |
CommonInst_Unpin(_) |
CommonInst_GetAddr(_) |
CommonInst_Tr64IsFp(_) |
CommonInst_Tr64IsInt(_) |
CommonInst_Tr64IsRef(_) |
CommonInst_Tr64FromFp(_) |
CommonInst_Tr64FromInt(_) |
CommonInst_Tr64FromRef(_, _) |
CommonInst_Tr64ToFp(_) |
CommonInst_Tr64ToInt(_) |
CommonInst_Tr64ToRef(_) |
CommonInst_Tr64ToTag(_) |
Move(_) |
PrintHex(_) |
SetRetval(_) => false,
Return(_) |
ThreadExit |
Throw(_) |
TailCall(_) |
Branch1(_) |
Branch2 { .. } |
Watchpoint { .. } |
WPBranch { .. } |
Call { .. } |
CCall { .. } |
SwapStack { .. } |
Switch { .. } |
ExnInstruction { .. } => true,
}
}
......@@ -138,13 +138,13 @@ impl Instruction {
BinOp(_, _, _) => false,
BinOpWithStatus(_, _, _, _) => false,
CmpOp(_, _, _) => false,
ConvOp{..} => false,
ExprCall{..} => true,
ExprCCall{..} => true,
Load{..} => true,
Store{..} => true,
CmpXchg{..} => true,
AtomicRMW{..} => true,
ConvOp { .. } => false,
ExprCall { .. } => true,
ExprCCall { .. } => true,
Load { .. } => true,
Store { .. } => true,
CmpXchg { .. } => true,
AtomicRMW { .. } => true,
New(_) => true,
AllocA(_) => true,
NewHybrid(_, _) => true,
......@@ -154,40 +154,36 @@ impl Instruction {
NewThreadExn(_, _) => true,
NewFrameCursor(_) => true,
GetIRef(_) => false,
GetFieldIRef{..} => false,
GetElementIRef{..} => false,
ShiftIRef{..} => false,
GetVarPartIRef{..} => false,
GetFieldIRef { .. } => false,
GetElementIRef { .. } => false,
ShiftIRef { .. } => false,
GetVarPartIRef { .. } => false,
Fence(_) => true,
Return(_) => true,
ThreadExit => true,
Throw(_) => true,
TailCall(_) => true,
Branch1(_) => true,
Branch2{..} => true,
Select{..} => false,
Watchpoint{..} => true,
WPBranch{..} => true,
Call{..} => true,
CCall{..} => true,
SwapStack{..} => true,
Switch{..} => true,
ExnInstruction{..} => true,
Branch2 { .. } => true,
Select { .. } => false,
Watchpoint { .. } => true,
WPBranch { .. } => true,
Call { .. } => true,
CCall { .. } => true,
SwapStack { .. } => true,
Switch { .. } => true,
ExnInstruction { .. } => true,
CommonInst_GetThreadLocal => true,
CommonInst_SetThreadLocal(_) => true,
CommonInst_Pin(_)
| CommonInst_Unpin(_)
| CommonInst_GetAddr(_) => true,
CommonInst_Tr64IsFp(_)
| CommonInst_Tr64IsInt(_)
| CommonInst_Tr64IsRef(_) => false,
CommonInst_Tr64FromFp(_)
| CommonInst_Tr64FromInt(_)
| CommonInst_Tr64FromRef(_, _) => false,
CommonInst_Tr64ToFp(_)
| CommonInst_Tr64ToInt(_)
| CommonInst_Tr64ToRef(_)
| CommonInst_Tr64ToTag(_) => false,
CommonInst_Pin(_) | CommonInst_Unpin(_) | CommonInst_GetAddr(_) => true,
CommonInst_Tr64IsFp(_) | CommonInst_Tr64IsInt(_) | CommonInst_Tr64IsRef(_) => false,
CommonInst_Tr64FromFp(_) | CommonInst_Tr64FromInt(_) | CommonInst_Tr64FromRef(_, _) => {
false
}
CommonInst_Tr64ToFp(_) |
CommonInst_Tr64ToInt(_) |
CommonInst_Tr64ToRef(_) |
CommonInst_Tr64ToTag(_) => false,
Move(_) => false,
PrintHex(_) => true,
SetRetval(_) => true,
......@@ -200,63 +196,63 @@ impl Instruction {
use inst::Instruction_::*;
match self.v {
Watchpoint{..}
| Call{..}
| CCall{..}
| SwapStack{..}
| ExnInstruction{..} => true,
BinOp(_, _, _)
| BinOpWithStatus(_, _, _, _)
| CmpOp(_, _, _)
| ConvOp{..}
| ExprCall{..}
| ExprCCall{..}
| Load{..}
| Store{..}
| CmpXchg{..}
| AtomicRMW{..}
| New(_)
| AllocA(_)
| NewHybrid(_, _)
| AllocAHybrid(_, _)
| NewStack(_)
| NewThread(_, _)
| NewThreadExn(_, _)
| NewFrameCursor(_)
| GetIRef(_)
| GetFieldIRef{..}
| GetElementIRef{..}
| ShiftIRef{..}
| GetVarPartIRef{..}
| Fence(_)
| Return(_)
| ThreadExit
| Throw(_)
| TailCall(_)
| Branch1(_)
| Branch2{..}
| Select{..}
| WPBranch{..}
| Switch{..}
| CommonInst_GetThreadLocal
| CommonInst_SetThreadLocal(_)
| CommonInst_Pin(_)
| CommonInst_Unpin(_)
| CommonInst_GetAddr(_)
| CommonInst_Tr64IsFp(_)
| CommonInst_Tr64IsInt(_)
| CommonInst_Tr64IsRef(_)
| CommonInst_Tr64FromFp(_)
| CommonInst_Tr64FromInt(_)
| CommonInst_Tr64FromRef(_, _)
| CommonInst_Tr64ToFp(_)
| CommonInst_Tr64ToInt(_)
| CommonInst_Tr64ToRef(_)
| CommonInst_Tr64ToTag(_)
| Move(_)
| PrintHex(_)
| SetRetval(_) => false
Watchpoint { .. } |
Call { .. } |
CCall { .. } |
SwapStack { .. } |
ExnInstruction { .. } => true,
BinOp(_, _, _) |
BinOpWithStatus(_, _, _, _) |
CmpOp(_, _, _) |
ConvOp { .. } |
ExprCall { .. } |
ExprCCall { .. } |
Load { .. } |
Store { .. } |
CmpXchg { .. } |
AtomicRMW { .. } |
New(_) |
AllocA(_) |
NewHybrid(_, _) |
AllocAHybrid(_, _) |
NewStack(_) |
NewThread(_, _) |
NewThreadExn(_, _) |
NewFrameCursor(_) |
GetIRef(_) |
GetFieldIRef { .. } |
GetElementIRef { .. } |
ShiftIRef { .. } |
GetVarPartIRef { .. } |
Fence(_) |
Return(_) |
ThreadExit |
Throw(_) |
TailCall(_) |
Branch1(_) |
Branch2 { .. } |
Select { .. } |
WPBranch { .. } |
Switch { .. } |
CommonInst_GetThreadLocal |
CommonInst_SetThreadLocal(_) |
CommonInst_Pin(_) |
CommonInst_Unpin(_) |
CommonInst_GetAddr(_) |
CommonInst_Tr64IsFp(_) |
CommonInst_Tr64IsInt(_) |
CommonInst_Tr64IsRef(_) |
CommonInst_Tr64FromFp(_) |
CommonInst_Tr64FromInt(_) |
CommonInst_Tr64FromRef(_, _) |
CommonInst_Tr64ToFp(_) |
CommonInst_Tr64ToInt(_) |
CommonInst_Tr64ToRef(_) |
CommonInst_Tr64ToTag(_) |
Move(_) |
PrintHex(_) |
SetRetval(_) => false,
}
}
......@@ -265,69 +261,68 @@ impl Instruction {
self.is_potentially_excepting_instruction()
}
/// returns exception target(block ID), returns None if this instruction does not have exceptional branch
/// returns exception target(block ID),
/// returns None if this instruction does not have exceptional branch
pub fn get_exception_target(&self) -> Option<MuID> {
use inst::Instruction_::*;
match self.v {
Watchpoint {ref resume, ..}
| Call {ref resume, ..}
| CCall {ref resume, ..}
| SwapStack {ref resume, ..}
| ExnInstruction {ref resume, ..} => {
Some(resume.exn_dest.target)
},
BinOp(_, _, _)
| BinOpWithStatus(_, _, _, _)
| CmpOp(_, _, _)
| ConvOp{..}
| ExprCall{..}
| ExprCCall{..}
| Load{..}
| Store{..}
| CmpXchg{..}
| AtomicRMW{..}
| New(_)
| AllocA(_)
| NewHybrid(_, _)
| AllocAHybrid(_, _)
| NewStack(_)
| NewThread(_, _)
| NewThreadExn(_, _)
| NewFrameCursor(_)
| GetIRef(_)
| GetFieldIRef{..}
| GetElementIRef{..}
| ShiftIRef{..}
| GetVarPartIRef{..}
| Fence(_)
| Return(_)
| ThreadExit
| Throw(_)
| TailCall(_)
| Branch1(_)
| Branch2{..}
| Select{..}
| WPBranch{..}
| Switch{..}
| CommonInst_GetThreadLocal
| CommonInst_SetThreadLocal(_)
| CommonInst_Pin(_)
| CommonInst_Unpin(_)
| CommonInst_GetAddr(_)
| CommonInst_Tr64IsFp(_)
| CommonInst_Tr64IsInt(_)
| CommonInst_Tr64IsRef(_)
| CommonInst_Tr64FromFp(_)
| CommonInst_Tr64FromInt(_)
| CommonInst_Tr64FromRef(_, _)
| CommonInst_Tr64ToFp(_)
| CommonInst_Tr64ToInt(_)
| CommonInst_Tr64ToRef(_)
| CommonInst_Tr64ToTag(_)
| Move(_)
| PrintHex(_)
| SetRetval(_) => None
Watchpoint { ref resume, .. } |
Call { ref resume, .. } |
CCall { ref resume, .. } |
SwapStack { ref resume, .. } |
ExnInstruction { ref resume, .. } => Some(resume.exn_dest.target),
BinOp(_, _, _) |
BinOpWithStatus(_, _, _, _) |
CmpOp(_, _, _) |
ConvOp { .. } |
ExprCall { .. } |
ExprCCall { .. } |
Load { .. } |
Store { .. } |
CmpXchg { .. } |
AtomicRMW { .. } |
New(_) |
AllocA(_) |
NewHybrid(_, _) |
AllocAHybrid(_, _) |
NewStack(_) |
NewThread(_, _) |
NewThreadExn(_, _) |
NewFrameCursor(_) |
GetIRef(_) |
GetFieldIRef { .. } |
GetElementIRef { .. } |
ShiftIRef { .. } |
GetVarPartIRef { .. } |
Fence(_) |
Return(_) |
ThreadExit |
Throw(_) |
TailCall(_) |
Branch1(_) |
Branch2 { .. } |
Select { .. } |
WPBranch { .. } |
Switch { .. } |
CommonInst_GetThreadLocal |
CommonInst_SetThreadLocal(_) |
CommonInst_Pin(_) |
CommonInst_Unpin(_) |
CommonInst_GetAddr(_) |
CommonInst_Tr64IsFp(_) |
CommonInst_Tr64IsInt(_) |
CommonInst_Tr64IsRef(_) |
CommonInst_Tr64FromFp(_) |
CommonInst_Tr64FromInt(_) |
CommonInst_Tr64FromRef(_, _) |
CommonInst_Tr64ToFp(_) |
CommonInst_Tr64ToInt(_) |
CommonInst_Tr64ToRef(_) |
CommonInst_Tr64ToTag(_) |
Move(_) |
PrintHex(_) |
SetRetval(_) => None,
}
}
......@@ -340,7 +335,12 @@ impl fmt::Display for Instruction {
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
let ref ops = self.ops;
if self.value.is_some() {
write!(f, "{} = {}", vec_utils::as_str(self.value.as_ref().unwrap()), self.v.debug_str(ops))
write!(
f,
"{} = {}",
vec_utils::as_str(self.value.as_ref().unwrap()),
self.v.debug_str(ops)
)
} else {
write!(f, "{}", self.v.debug_str(ops))
}
......@@ -352,7 +352,6 @@ impl fmt::Display for Instruction {
#[derive(Debug, Clone)]
pub enum Instruction_ {
// non-terminal instruction
/// binary operations
BinOp(BinOp, OpIndex, OpIndex),
/// binary operations with status flag (overflow, sign, etc. )
......@@ -362,60 +361,57 @@ pub enum Instruction_ {
CmpOp(CmpOp, OpIndex, OpIndex),
/// conversion operations (casting)
ConvOp{
ConvOp {
operation: ConvOp,
from_ty: P<MuType>,
to_ty: P<MuType>,
operand: OpIndex
operand: OpIndex,
},
/// a non-terminating Call instruction (the call does not have an exceptional branch)
/// This instruction is not in the Mu spec, but is documented in the HOL formal spec
ExprCall{
ExprCall {
data: CallData,
is_abort: bool, // T to abort, F to rethrow
},
/// a non-terminating CCall instruction (the call does not have an exceptional branch)
/// This instruction is not in the Mu spec, but is documented in the HOL formal spec
ExprCCall{
data: CallData,
is_abort: bool
},
ExprCCall { data: CallData, is_abort: bool },
/// load instruction
Load{
Load {
is_ptr: bool,
order: MemoryOrder,
mem_loc: OpIndex
mem_loc: OpIndex,
},
/// store instruction
Store{
Store {
is_ptr: bool,
order: MemoryOrder,
mem_loc: OpIndex,
value: OpIndex
value: OpIndex,
},
/// compare and exchange, yields a pair value (oldvalue, boolean (T = success, F = failure))
CmpXchg{
CmpXchg {
is_ptr: bool,
is_weak: bool,
success_order: MemoryOrder,
fail_order: MemoryOrder,
mem_loc: OpIndex,
expected_value: OpIndex,
desired_value: OpIndex
desired_value: OpIndex,
},
/// atomic read-modify-write, yields old memory value
AtomicRMW{
AtomicRMW {
is_ptr: bool, // T for iref, F for ptr
order: MemoryOrder,
op: AtomicRMWOp,
mem_loc: OpIndex,
value: OpIndex // operand for op
value: OpIndex, // operand for op
},
/// allocate an object (non hybrid type) in the heap, yields a reference of the type
......@@ -453,37 +449,33 @@ pub enum Instruction_ {
GetIRef(OpIndex),
/// get internal reference of an iref (or uptr) to a struct/hybrid fix part
GetFieldIRef{
GetFieldIRef {
is_ptr: bool,
base: OpIndex, // iref or uptr
index: usize // constant
index: usize, // constant
},
/// get internal reference of an element of an iref (or uptr) to an array
GetElementIRef{
GetElementIRef {
is_ptr: bool,
base: OpIndex,
index: OpIndex // can be constant or ssa var
index: OpIndex, // can be constant or ssa var
},
/// offset an iref (or uptr) (offset is an index)
ShiftIRef{
ShiftIRef {
is_ptr: bool,
base: OpIndex,
offset: OpIndex
offset: OpIndex,
},