Commit 91ae5641 authored by qinsoon's avatar qinsoon

[wip]

parent d5e8b432
......@@ -296,6 +296,13 @@ impl MuType {
}
}
pub fn is_uptr(&self) -> bool {
match self.v {
MuType_::UPtr(_) => true,
_ => false
}
}
/// is this type an aggregated type? (consisted of other types)
pub fn is_aggregate(&self) -> bool {
match self.v {
......
......@@ -1415,7 +1415,7 @@ impl ASMCodeGen {
op: &P<Value>,
loc: usize
) -> (String, LinkedHashMap<MuID, Vec<ASMLocation>>) {
debug_assert!(op.is_mem());
debug_assert!(op.is_mem(), "op is not mem: {}", op);
// temps/regs used
let mut ids: Vec<MuID> = vec![];
......@@ -1731,8 +1731,8 @@ impl ASMCodeGen {
let inst = inst.to_string() + &op_postfix(len);
trace!("emit: {} {} {}", inst, op1, op2);
let (mem, mut uses) = self.prepare_mem(op2, inst.len() + 1);
let (reg, id1, loc1) = self.prepare_reg(op1, inst.len() + 1 + mem.len() + 1);
let (reg, id1, loc1) = self.prepare_reg(op1, inst.len() + 1);
let (mem, mut uses) = self.prepare_mem(op2, inst.len() + 1 + reg.len() + 1);
if uses.contains_key(&id1) {
let mut locs = uses.get_mut(&id1).unwrap();
......@@ -1741,7 +1741,7 @@ impl ASMCodeGen {
uses.insert(id1, vec![loc1.clone()]);
}
let asm = format!("{} {},{}", inst, mem, reg);
let asm = format!("{} {},{}", inst, reg, mem);
self.add_asm_inst(asm, linked_hashmap!{}, uses, true)
}
......@@ -2254,7 +2254,7 @@ impl ASMCodeGen {
}
/// emits an instruction (use 1 fpreg 1 memory operand, define 1st fpreg)
fn internal_fp_binop_def_r_mem(&mut self, inst: &str, dest: Reg, src: Reg) {
fn internal_fp_binop_def_r_mem(&mut self, inst: &str, dest: Reg, src: Mem) {
trace!("emit: {} {}, {} -> {}", inst, src, dest, dest);
let (mem, mut uses) = self.prepare_mem(src, inst.len() + 1);
......
......@@ -5149,7 +5149,7 @@ impl<'a> InstructionSelection {
let mem_op1 = self.emit_mem(op1, f_content, f_context, vm);
let reg_op2 = self.emit_ireg(op2, f_content, f_context, vm);
self.backend.emit_cmp_r_mem(&mem_op1, &reg_op2);
self.backend.emit_cmp_r_mem(&reg_op2, &mem_op1);
return op;
} else if self.match_ireg(op1) && self.match_ireg(op2) {
......@@ -5554,15 +5554,13 @@ impl<'a> InstructionSelection {
match pv.v {
Value_::SSAVar(_) => pv.clone(),
Value_::Constant(Constant::Double(_)) => {
let mem = self.get_mem_for_const(pv, vm);
let tmp_fp = self.make_temporary(f_context, DOUBLE_TYPE.clone(), vm);
self.backend.emit_movsd_f64_mem64(&tmp_fp, &mem);
self.emit_move_value_to_value(&tmp_fp, pv, f_context, vm);
tmp_fp
}
Value_::Constant(Constant::Float(_)) => {
let mem = self.get_mem_for_const(pv, vm);
let tmp_fp = self.make_temporary(f_context, FLOAT_TYPE.clone(), vm);
self.backend.emit_movss_f32_mem32(&tmp_fp, &mem);
self.emit_move_value_to_value(&tmp_fp, pv, f_context, vm);
tmp_fp
}
_ => panic!("expected fpreg")
......@@ -6164,11 +6162,20 @@ impl<'a> InstructionSelection {
_ => panic!("cannot get MEM from general ireg inst: {}", op)
}
}
_ => {
panic!(
"expected an instruction that yields a memory address, found {}",
op
)
TreeNode_::Value(ref pv) => {
if pv.ty.is_heap_reference() || pv.ty.is_uptr() {
MemoryLocation::Address {
base: pv.clone(),
offset: None,
index: None,
scale: None
}
} else {
panic!(
"expected a value that yields a memory address, found {}",
op
)
}
}
}
}
......
......@@ -1401,8 +1401,10 @@ def test_float():
points = [None] * n
for i in xrange(n):
points[i] = Point(i)
print points[i]
for p in points:
p.normalize()
print p
return maximize(points)
POINTS = 100
......
# Copyright 2017 The Australian National University
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
from util import execute, compile_bundle, load_bundle, get_function;
import pytest;
import ctypes;
def test_gt_mem_r():
lib = load_bundle(
"""
.funcsig sig = (int<64> uptr<int<64>>) -> (int<64>)
.funcdef test_gt_mem_r <sig>
{
entry(<int<64>> x <uptr<int<64>>> ptr):
y = LOAD PTR <int<64>> ptr
cond = SGT <int<64>> x y
BRANCH2 cond ret1() ret0()
ret1():
RET <int<64>> 1
ret0():
RET <int<64>> 0
}
""", "test_gt_mem_r"
)
zero = ctypes.c_int64(0);
ptr = ctypes.addressof(zero);
cmp_gt_zero = get_function(lib.test_gt_mem_r, [ctypes.c_int64, ctypes.c_int64], ctypes.c_int64)
assert(cmp_gt_zero(ctypes.c_int64(1), ptr) == 1)
assert(cmp_gt_zero(ctypes.c_int64(0), ptr) == 0)
assert(cmp_gt_zero(ctypes.c_int64(-1), ptr) == 0)
def test_gt_val_mem_r():
lib = load_bundle(
"""
.funcsig sig = (int<64> uptr<int<64>>) -> (int<8>)
.funcdef test_gt_val_mem_r <sig>
{
entry(<int<64>> x <uptr<int<64>>> ptr):
y = LOAD PTR <int<64>> ptr
cond = SGT <int<64>> x y
res = ZEXT <int<1> int<8>> cond
RET res
}
""", "test_gt_val_mem_r"
)
zero = ctypes.c_int64(0);
ptr = ctypes.addressof(zero);
cmp_gt_zero = get_function(lib.test_gt_val_mem_r, [ctypes.c_int64, ctypes.c_voidp], ctypes.c_int8)
assert(cmp_gt_zero(ctypes.c_int64(1), ptr) == 1)
assert(cmp_gt_zero(ctypes.c_int64(0), ptr) == 0)
assert(cmp_gt_zero(ctypes.c_int64(-1), ptr) == 0)
def test_gt_r_mem():
lib = load_bundle(
"""
.funcsig sig = (uptr<int<64>> int<64>) -> (int<64>)
.funcdef test_gt_r_mem <sig>
{
entry(<uptr<int<64>>> ptr <int<64>> y):
x = LOAD PTR <int<64>> ptr
cond = SGT <int<64>> x y
BRANCH2 cond ret1() ret0()
ret1():
RET <int<64>> 1
ret0():
RET <int<64>> 0
}
""", "test_gt_r_mem"
)
zero = ctypes.c_int64(0);
ptr = ctypes.addressof(zero);
cmp_gt_zero = get_function(lib.test_gt_r_mem, [ctypes.c_int64, ctypes.c_int64], ctypes.c_int64)
assert(cmp_gt_zero(ptr, ctypes.c_int64(1)) == 0)
assert(cmp_gt_zero(ptr, ctypes.c_int64(0)) == 0)
assert(cmp_gt_zero(ptr, ctypes.c_int64(-1)) == 1)
def test_gt_mem_f():
lib = load_bundle(
"""
.funcsig sig = (double uptr<double>) -> (int<64>)
.funcdef test_gt_mem_f <sig>
{
entry(<double> x <uptr<double>> ptr):
y = LOAD PTR <double> ptr
cond = FOGT <double> x y
BRANCH2 cond ret1() ret0()
ret1():
RET <int<64>> 1
ret0():
RET <int<64>> 0
}
""", "test_gt_mem_f"
)
zero = ctypes.c_double(0);
ptr = ctypes.addressof(zero);
cmp_gt_zero = get_function(lib.test_gt_mem_f, [ctypes.c_double, ctypes.c_voidp], ctypes.c_int64)
assert(cmp_gt_zero(ctypes.c_double(1), ptr) == 1)
assert(cmp_gt_zero(ctypes.c_double(0), ptr) == 0)
assert(cmp_gt_zero(ctypes.c_double(-1), ptr) == 0)
def test_gt_f_mem():
lib = load_bundle(
"""
.funcsig sig = (uptr<double> double) -> (int<64>)
.funcdef test_gt_f_mem <sig>
{
entry(<uptr<double>> ptr <double> y):
x = LOAD PTR <double> ptr
cond = FOGT <double> x y
BRANCH2 cond ret1() ret0()
ret1():
RET <int<64>> 1
ret0():
RET <int<64>> 0
}
""", "test_gt_f_mem"
)
zero = ctypes.c_double(0);
ptr = ctypes.addressof(zero);
cmp_gt_zero = get_function(lib.test_gt_f_mem, [ctypes.c_voidp, ctypes.c_double], ctypes.c_int64)
assert(cmp_gt_zero(ptr, ctypes.c_double(1)) == 0)
assert(cmp_gt_zero(ptr, ctypes.c_double(0)) == 0)
assert(cmp_gt_zero(ptr, ctypes.c_double(-1)) == 1)
def test_eq_f_zero():
lib = load_bundle(
"""
.funcsig sig = (double) -> (int<8>)
.funcdef test_eq_f_zero <sig>
{
entry(<double> x):
cond = FOEQ <double> x <double> 0.00 d
res = ZEXT <int<1> int<8>> cond
RET res
}
""", "test_eq_f_zero"
)
eq_zero = get_function(lib.test_eq_f_zero, [ctypes.c_double], ctypes.c_int8)
assert(eq_zero(ctypes.c_double(0)) == 1)
assert(eq_zero(ctypes.c_double(1)) == 0)
assert(eq_zero(ctypes.c_double(-1)) == 0)
\ No newline at end of file
......@@ -239,5 +239,4 @@ def test_exc_pass_values():
}
""", "test_exc_pass_values");
assert(execute("test_exc_pass_values") == 4);
assert(execute("test_exc_pass_values") == 4);
\ No newline at end of file
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