Commit 94d6c0a0 authored by qinsoon's avatar qinsoon

[wip] add cfi info

parent 97d44cf2
......@@ -1997,6 +1997,25 @@ impl CodeGenerator for ASMCodeGen {
}
}
fn add_cfi_startproc(&mut self) {
self.add_asm_symbolic(".cfi_startproc".to_string());
}
fn add_cfi_endproc(&mut self) {
self.add_asm_symbolic(".cfi_endproc".to_string());
}
fn add_cfi_def_cfa_register(&mut self, reg: Reg) {
let reg = self.asm_reg_op(reg);
self.add_asm_symbolic(format!(".cfi_def_cfa_register {}", reg));
}
fn add_cfi_def_cfa_offset(&mut self, offset: i32) {
self.add_asm_symbolic(format!(".cfi_def_cfa_offset {}", offset));
}
fn add_cfi_offset(&mut self, reg: Reg, offset: i32) {
let reg = self.asm_reg_op(reg);
self.add_asm_symbolic(format!(".cfi_offset {}, {}", reg, offset));
}
fn emit_frame_grow(&mut self) {
trace!("emit frame grow");
......
......@@ -21,6 +21,14 @@ pub trait CodeGenerator {
fn set_block_liveout(&mut self, block_name: MuName, live_out: &Vec<P<Value>>);
fn end_block(&mut self, block_name: MuName);
// add CFI info
fn add_cfi_startproc(&mut self);
fn add_cfi_endproc(&mut self);
fn add_cfi_def_cfa_register(&mut self, reg: Reg);
fn add_cfi_def_cfa_offset(&mut self, offset: i32);
fn add_cfi_offset(&mut self, reg: Reg, offset: i32);
// emit code to adjust frame
fn emit_frame_grow(&mut self);
fn emit_frame_shrink(&mut self);
......
......@@ -2617,8 +2617,16 @@ impl <'a> InstructionSelection {
// push rbp
self.backend.emit_push_r64(&x86_64::RBP);
if vm.vm_options.flag_emit_debug_info {
self.backend.add_cfi_def_cfa_offset(16i32);
self.backend.add_cfi_offset(&x86_64::RBP, -16i32);
}
// mov rsp -> rbp
self.backend.emit_mov_r_r(&x86_64::RBP, &x86_64::RSP);
if vm.vm_options.flag_emit_debug_info {
self.backend.add_cfi_def_cfa_register(&x86_64::RBP);
}
// push all callee-saved registers
{
......@@ -3637,7 +3645,12 @@ impl CompilerPass for InstructionSelection {
self.current_func_start = Some({
let funcs = vm.funcs().read().unwrap();
let func = funcs.get(&func_ver.func_id).unwrap().read().unwrap();
self.backend.start_code(func.name().unwrap(), entry_block.name().unwrap())
let start_loc = self.backend.start_code(func.name().unwrap(), entry_block.name().unwrap());
if vm.vm_options.flag_emit_debug_info {
self.backend.add_cfi_startproc();
}
start_loc
});
self.current_callsite_id = 0;
self.current_exn_callsites.clear();
......@@ -3722,7 +3735,11 @@ impl CompilerPass for InstructionSelection {
let func = funcs.get(&func.func_id).unwrap().read().unwrap();
func.name().unwrap()
};
// have to do this before 'finish_code()'
if vm.vm_options.flag_emit_debug_info {
self.backend.add_cfi_endproc();
}
let (mc, func_end) = self.backend.finish_code(func_name.clone());
// insert exception branch info
......
......@@ -17,6 +17,7 @@ VM:
Compiler:
--disable-inline disable compiler function inlining
--disable-regalloc-validate disable register allocation validation
--emit-debug-info emit debugging information
AOT Compiler:
--aot-emit-dir=<dir> the emit directory for ahead-of-time compiling [default: emit]
......@@ -33,14 +34,20 @@ Garbage Collection:
#[derive(Debug, RustcDecodable, RustcEncodable)]
pub struct VMOptions {
// VM
pub flag_log_level: MuLogLevel,
// Compiler
pub flag_disable_inline: bool,
pub flag_disable_regalloc_validate: bool,
pub flag_emit_debug_info: bool,
// AOT compiler
pub flag_aot_emit_dir: String,
pub flag_bootimage_external_lib: Vec<String>,
pub flag_bootimage_external_libpath: Vec<String>,
// GC
pub flag_gc_disable_collection: bool,
pub flag_gc_immixspace_size: usize,
pub flag_gc_lospace_size: usize,
......@@ -64,6 +71,8 @@ impl VMOptions {
// at the moment disable collection for debugging
ret.flag_gc_disable_collection = true;
// at the moment always emit debug info
ret.flag_emit_debug_info = true;
ret
}
......
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