1. 17 Oct, 2017 1 commit
  2. 16 Oct, 2017 1 commit
  3. 13 Oct, 2017 2 commits
  4. 12 Oct, 2017 1 commit
  5. 10 Oct, 2017 1 commit
  6. 21 Sep, 2017 1 commit
  7. 15 Sep, 2017 3 commits
  8. 29 Aug, 2017 1 commit
  9. 23 Jul, 2017 3 commits
  10. 20 Jul, 2017 1 commit
  11. 19 Jul, 2017 1 commit
  12. 14 Jul, 2017 2 commits
  13. 29 Jun, 2017 1 commit
  14. 27 Jun, 2017 2 commits
  15. 16 Jun, 2017 1 commit
  16. 15 Jun, 2017 1 commit
  17. 03 May, 2017 1 commit
  18. 17 Mar, 2017 1 commit
  19. 17 Feb, 2017 1 commit
  20. 01 Feb, 2017 1 commit
  21. 31 Jan, 2017 1 commit
  22. 30 Jan, 2017 1 commit
  23. 08 Dec, 2016 1 commit
  24. 04 Dec, 2016 1 commit
  25. 24 Nov, 2016 1 commit
    • qinsoon's avatar
      fixed a few problems · 751795b1
      qinsoon authored
      1. asm call do not use all argument registers (otherwise it will keep
      them alive)
      2. spilling a register that is used and defined in one instruction will
      result in creating one new temporary, instead of two
      3. spilling now deals with floating point
      4. SELECT with int8 is implemented using conditional jump (cmov cannot
      take reg8)
      5. postcall convention now deals correctly with fp return values
      6. reg alloc conservative() was wrong in a few commits ago, fixed it
      7. in liveness analysis, when finding a move between a temp and a
      register, find the color for the register (such as RAX for EAX)
      751795b1
  26. 23 Nov, 2016 1 commit
    • qinsoon's avatar
      fix test_extern_func · 62870f1f
      qinsoon authored
      when we add interefence between %a and %edi, we also add %a with %rdi
      because we cannot assign rdi to a
      62870f1f
  27. 22 Nov, 2016 2 commits
  28. 18 Nov, 2016 1 commit
    • qinsoon's avatar
      add VMOptions · f79120b2
      qinsoon authored
      1. see vm/vm_options.rs for usage and default values
      2. added mu_fastimpl_new_with_opts under vm/api/api_impl/muvm.rs
      f79120b2
  29. 17 Nov, 2016 1 commit
  30. 16 Nov, 2016 1 commit
    • qinsoon's avatar
      fix · 4464d5a5
      qinsoon authored
      4464d5a5
  31. 15 Nov, 2016 1 commit
    • qinsoon's avatar
      start using 8/16/32 bits registers · 38d18dda
      qinsoon authored
      1. compiler knows all the registers
      2. but only 64bits register is a color (for reg alloc)
      3. backend records the length of GPR for each operand during instruction
      selection
      4. after reg alloc, when replacing temp with a color, find corresponding
      GPR for the length recorded before
      38d18dda
  32. 11 Nov, 2016 1 commit