1. 19 Jul, 2017 1 commit
  2. 10 Jul, 2017 1 commit
  3. 09 Jul, 2017 1 commit
  4. 16 Jun, 2017 1 commit
  5. 07 Jun, 2017 1 commit
  6. 05 Jun, 2017 2 commits
  7. 11 May, 2017 1 commit
  8. 09 May, 2017 1 commit
  9. 04 May, 2017 2 commits
  10. 01 May, 2017 2 commits
  11. 03 Apr, 2017 1 commit
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  18. 19 Jan, 2017 1 commit
  19. 07 Jan, 2017 1 commit
  20. 24 Nov, 2016 2 commits
  21. 23 Nov, 2016 1 commit
    • qinsoon's avatar
      fp add with two constants · 443d866a
      qinsoon authored
      currently mov constant as imm to a GPR, then mov from GPR
      to xmm. A better approach should be put the immediate in memroy,
      and load it
      443d866a
  22. 16 Nov, 2016 1 commit
  23. 15 Nov, 2016 1 commit
    • qinsoon's avatar
      start using 8/16/32 bits registers · 38d18dda
      qinsoon authored
      1. compiler knows all the registers
      2. but only 64bits register is a color (for reg alloc)
      3. backend records the length of GPR for each operand during instruction
      selection
      4. after reg alloc, when replacing temp with a color, find corresponding
      GPR for the length recorded before
      38d18dda
  24. 14 Nov, 2016 2 commits
  25. 11 Nov, 2016 1 commit
  26. 04 Nov, 2016 1 commit
    • qinsoon's avatar
      fib in test-jit runs · 5b723a45
      qinsoon authored
      1. grow/shrink frame size in the pro/epilogue. Note: though we removed
      push/pop for unused callee saved registers, we still reserve frame space
      for them. Because we generate spill on frame before we know exactly how
      large a space is. The solution is to make spill locations patchable.
      2. control flow will combine branches in switch instruction if they all
      target the same destination.
      5b723a45
  27. 03 Nov, 2016 3 commits
  28. 02 Nov, 2016 1 commit
  29. 01 Nov, 2016 1 commit
  30. 31 Oct, 2016 3 commits
  31. 28 Oct, 2016 1 commit
    • qinsoon's avatar
      sdiv · 4b0515a0
      qinsoon authored
      4b0515a0