Commit 6dbde1d3 authored by Kunshan Wang's avatar Kunshan Wang

Test vector binary op.

parent 235fdab5
......@@ -44,9 +44,12 @@ class InterpreterThread(val id: Int, microVM: MicroVM, initialStack: Interpreter
case l: LocalVariable => top.boxes(l)
}
def ctx = "FuncVer %s, BasicBlock %s, Instruction %s (%s): ".format(top.funcVer.repr, curBB.repr, curInst.repr, curInst.getClass.getName)
def ctx = stack match {
case None => "(Thred not bound to stack): "
case Some(_) => "FuncVer %s, BasicBlock %s, Instruction %s (%s): ".format(top.funcVer.repr, curBB.repr, curInst.repr, curInst.getClass.getName)
}
private def interpretCurrentInstruction(): Unit = {
private def interpretCurrentInstruction(): Unit = try {
val curInst = this.curInst
logger.debug(ctx + "Executing instruction...")
......@@ -59,7 +62,7 @@ class InterpreterThread(val id: Int, microVM: MicroVM, initialStack: Interpreter
val result = PrimOpHelpers.intBinOp(op, l, op1v, op2v, ctx)
val iBox = boxOf(i).asInstanceOf[BoxInt]
val iBox = br.asInstanceOf[BoxInt]
iBox.value = result
}
......@@ -69,7 +72,7 @@ class InterpreterThread(val id: Int, microVM: MicroVM, initialStack: Interpreter
val result = PrimOpHelpers.floatBinOp(op, op1v, op2v, ctx)
val iBox = boxOf(i).asInstanceOf[BoxFloat]
val iBox = br.asInstanceOf[BoxFloat]
iBox.value = result
}
......@@ -79,7 +82,7 @@ class InterpreterThread(val id: Int, microVM: MicroVM, initialStack: Interpreter
val result = PrimOpHelpers.doubleBinOp(op, op1v, op2v, ctx)
val iBox = boxOf(i).asInstanceOf[BoxDouble]
val iBox = br.asInstanceOf[BoxDouble]
iBox.value = result
}
......@@ -96,7 +99,7 @@ class InterpreterThread(val id: Int, microVM: MicroVM, initialStack: Interpreter
opndTy match {
case TypeVector(scalarTy, sz) => {
val op1Bs = boxOf(op1).asInstanceOf[BoxVector].values
val op2Bs = boxOf(op1).asInstanceOf[BoxVector].values
val op2Bs = boxOf(op2).asInstanceOf[BoxVector].values
val rBs = boxOf(i).asInstanceOf[BoxVector].values
for (((b1, b2), br) <- ((op1Bs zip op2Bs) zip rBs)) {
......@@ -157,7 +160,7 @@ class InterpreterThread(val id: Int, microVM: MicroVM, initialStack: Interpreter
opndTy match {
case TypeVector(scalarTy, sz) => {
val op1Bs = boxOf(op1).asInstanceOf[BoxVector].values
val op2Bs = boxOf(op1).asInstanceOf[BoxVector].values
val op2Bs = boxOf(op2).asInstanceOf[BoxVector].values
val rBs = boxOf(i).asInstanceOf[BoxVector].values
for (((b1, b2), br) <- ((op1Bs zip op2Bs) zip rBs)) {
......@@ -361,11 +364,16 @@ class InterpreterThread(val id: Int, microVM: MicroVM, initialStack: Interpreter
}
}
case i => {
throw new UvmRefImplException("Unimplemented instruction %s".format(i.getClass.getName))
}
}
} catch {
case e: Exception => {
logger.debug(ctx + "Exception thrown while interpreting instruction.")
throw e
}
}
def branchAndMovePC(dest: BasicBlock, excAddr: Word = 0L): Unit = {
......
......@@ -83,7 +83,7 @@ object ValueBox {
case _: TypeInt => BoxInt(0)
case _: TypeFloat => BoxFloat(0.0f)
case _: TypeDouble => BoxDouble(0.0d)
case TypeVector(elemTy, len) => BoxVector(Seq.fill(4)(makeBoxForType(elemTy)))
case TypeVector(elemTy, len) => BoxVector(Seq.fill(len.toInt)(makeBoxForType(elemTy)))
case _: TypeRef => BoxRef(0L)
case _: TypeIRef => BoxIRef(0L, 0L)
case _: TypeWeakRef => throw new UvmRefImplException("weakref cannot be an SSA variable type")
......
This diff is collapsed.
......@@ -175,6 +175,23 @@
COMMINST @uvm.thread_exit
}
.funcsig @binops_vec_sig = @void (@4xi32 @4xi32 @4xfloat @4xfloat @2xdouble @2xdouble)
.funcdef @binops_vec VERSION @binops_vec_v1 <@binops_vec_sig> (%p0 %p1 %p2 %p3 %p4 %p5) {
%entry:
%addi = ADD <@4xi32> %p0 %p1
%subi = SUB <@4xi32> %p0 %p1
%addf = FADD <@4xfloat> %p2 %p3
%subf = FSUB <@4xfloat> %p2 %p3
%addd = FADD <@2xdouble> %p4 %p5
%subd = FSUB <@2xdouble> %p4 %p5
%trap = TRAP <@void> KEEPALIVE (
%addi %subi %addf %subf %addd %subd
)
COMMINST @uvm.thread_exit
}
.funcsig @cmp64_sig = @void (@i64 @i64)
.funcdef @cmp64 VERSION @cmp64_v1 <@cmp64_sig> (%p0 %p1) {
%entry:
......
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