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Commit ed7707c2 authored by Kunshan Wang's avatar Kunshan Wang
Browse files

Updated basic data structures.

parent 5230f706
...@@ -165,7 +165,7 @@ instBody ...@@ -165,7 +165,7 @@ instBody
dis=bbName ena=bbName ('WPEXC' '(' wpExc=bbName ')')? keepAliveClause # InstWatchPoint dis=bbName ena=bbName ('WPEXC' '(' wpExc=bbName ')')? keepAliveClause # InstWatchPoint
// Foreign Function Interface // Foreign Function Interface
| 'CCALL' '<' type '>' callconv funcCallBody # InstCCall | 'CCALL' '<' funcTy=type funcSig '>' callconv funcCallBody # InstCCall
// Thread and Stack Operations // Thread and Stack Operations
| 'NEWSTACK' funcCallBody excClause # InstNewStack | 'NEWSTACK' funcCallBody excClause # InstNewStack
......
package uvm package uvm
import uvm.types._ import uvm.types._
import uvm.ssavalues._ import uvm.ssavariables._
class Bundle { class Bundle {
val typeNs = new SimpleNamespace[Type]() val typeNs = new SimpleNamespace[Type]()
......
package uvm
import uvm.types._
case class GlobalData(var ty: Type) extends IdentifiedSettable
package uvm.comminsts
import uvm._
case class CommInst(val id: Int, val name: Option[String]) extends Identified
object CommInsts extends SimpleNamespace[CommInst] {
private def commInst(id: Int, name: String) {
val ci = CommInst(id, Some(name))
add(ci)
}
commInst(0x201, "@uvm.new_thread")
commInst(0x202, "@uvm.kill_stack")
commInst(0x203, "@uvm.thread_exit")
commInst(0x204, "@uvm.current_stack")
commInst(0x211, "@uvm.tr64.is_fp")
commInst(0x212, "@uvm.tr64.is_int")
commInst(0x213, "@uvm.tr64.is_ref")
commInst(0x214, "@uvm.tr64.from_fp")
commInst(0x215, "@uvm.tr64.from_int")
commInst(0x216, "@uvm.tr64.from_ref")
commInst(0x217, "@uvm.tr64.to_fp")
commInst(0x218, "@uvm.tr64.to_int")
commInst(0x219, "@uvm.tr64.to_ref")
commInst(0x21a, "@uvm.tr64.to_tag")
commInst(0x220, "@uvm.futex.wait")
commInst(0x221, "@uvm.futex.wake")
}
\ No newline at end of file
package uvm package uvm
import uvm.types._ import uvm.types._
import uvm.ssavalues._ import uvm.ssavariables._
case class FuncSig(var retTy: Type, var paramTy: Seq[Type]) extends IdentifiedSettable case class FuncSig(var retTy: Type, var paramTy: Seq[Type]) extends IdentifiedSettable
...@@ -10,19 +10,21 @@ object FuncSig { ...@@ -10,19 +10,21 @@ object FuncSig {
"%s (%s)".format(sig.retTy.repr, sig.paramTy.map(_.repr).mkString(" ")) "%s (%s)".format(sig.retTy.repr, sig.paramTy.map(_.repr).mkString(" "))
} }
class Function extends IdentifiedSettable { class Function extends GlobalVariable {
var sig: FuncSig = null var sig: FuncSig = null
var cfg: Option[CFG] = None var versions: Seq[FuncVersion] = Nil
} }
class CFG { /**
* A version of a function. Also known as a "control flow graph".
*/
class FuncVersion extends IdentifiedSettable {
var func: Function = null var func: Function = null
var bbs: Seq[BasicBlock] = null var bbs: Seq[BasicBlock] = null
var entry: BasicBlock = null var entry: BasicBlock = null
var params: Seq[Parameter] = null var params: Seq[Parameter] = null
val bbNs: Namespace[BasicBlock] = new SimpleNamespace[BasicBlock] // Consider using one global bb ns val bbNs: Namespace[BasicBlock] = new SimpleNamespace[BasicBlock]
val lvNs: Namespace[LocalValue] = new SimpleNamespace[LocalValue] // Consider using one global value ns
} }
class BasicBlock extends IdentifiedSettable { class BasicBlock extends IdentifiedSettable {
......
package uvm.ifuncs
import uvm._
import uvm.types._
import uvm.types.CommonTypes._
case class IFunc(val id: Int, val name: Option[String], val sig: FuncSig) extends Identified {
def ty = sig.retTy
}
object IFuncs extends SimpleNamespace[IFunc] {
private def addIFunc(id: Int, name: String, retTy: Type, paramTy: Seq[Type]): IFunc = {
val iFunc = IFunc(id, Some(name), FuncSig(retTy, paramTy))
add(iFunc)
return iFunc
}
val UVM_NEW_THREAD = addIFunc(0x201, "@uvm.new_thread", VOID, Seq(THREAD))
val UVM_SWAP_STACK = addIFunc(0x202, "@uvm.swap_stack", VOID, Seq(STACK))
val UVM_KILL_STACK = addIFunc(0x203, "@uvm.kill_stack", VOID, Seq(STACK))
val UVM_SWAP_AND_KILL = addIFunc(0x204, "@uvm.swap_and_kill", VOID, Seq(STACK))
val UVM_THREAD_EXIT = addIFunc(0x205, "@uvm.thread_exit", VOID, Seq(THREAD))
val UVM_MATH_SIN = addIFunc(0x101, "@uvm.math.sin", DOUBLE, Seq(DOUBLE))
}
\ No newline at end of file
...@@ -4,8 +4,8 @@ import scala.collection.JavaConversions._ ...@@ -4,8 +4,8 @@ import scala.collection.JavaConversions._
import uvm._ import uvm._
import uvm.types._ import uvm.types._
import uvm.ssavalues._ import uvm.ssavariables._
import uvm.ifuncs._ import uvm.comminsts._
import uvm.ir.textinput.gen._ import uvm.ir.textinput.gen._
import org.antlr.v4.runtime._ import org.antlr.v4.runtime._
import org.antlr.v4.runtime.tree.TerminalNode import org.antlr.v4.runtime.tree.TerminalNode
......
package uvm.ir.textinput
import scala.util.parsing.combinator.RegexParsers
object UvmIRParser extends RegexParsers {
import UvmIRAST._
implicit class ParserExtension[T](that: Parser[T]) {
def ~<[U](q: => Parser[U]): Parser[T] = {
lazy val p = q // lazy argument
(for (a <- that; b <- p) yield a).named("~<")
}
}
implicit class ParserMap2[T1, T2](that: Parser[T1 ~ T2]) {
def ^^^^[U](f: (T1, T2) => U): Parser[U] = that ^^ { case t1 ~ t2 => f(t1, t2) }
}
implicit class ParserMap3[T1, T2, T3](that: Parser[T1 ~ T2 ~ T3]) {
def ^^^^[U](f: (T1, T2, T3) => U): Parser[U] = that ^^ { case t1 ~ t2 ~ t3 => f(t1, t2, t3) }
}
implicit class ParserMap4[T1, T2, T3, T4](that: Parser[T1 ~ T2 ~ T3 ~ T4]) {
def ^^^^[U](f: (T1, T2, T3, T4) => U): Parser[U] = that ^^ { case t1 ~ t2 ~ t3 ~ t4 => f(t1, t2, t3, t4) }
}
implicit class ParserMap5[T1, T2, T3, T4, T5](that: Parser[T1 ~ T2 ~ T3 ~ T4 ~ T5]) {
def ^^^^[U](f: (T1, T2, T3, T4, T5) => U): Parser[U] = that ^^ { case t1 ~ t2 ~ t3 ~ t4 ~ t5 => f(t1, t2, t3, t4, t5) }
}
implicit class ParserMap6[T1, T2, T3, T4, T5, T6](that: Parser[T1 ~ T2 ~ T3 ~ T4 ~ T5 ~ T6]) {
def ^^^^[U](f: (T1, T2, T3, T4, T5, T6) => U): Parser[U] = that ^^ { case t1 ~ t2 ~ t3 ~ t4 ~ t5 ~ t6 => f(t1, t2, t3, t4, t5, t6) }
}
def ang[T](q: => Parser[T]): Parser[T] = { lazy val p = q; "<" ~> p <~ ">" }
def paren[T](q: => Parser[T]): Parser[T] = { lazy val p = q; "(" ~> p <~ ")" }
def brace[T](q: => Parser[T]): Parser[T] = { lazy val p = q; "{" ~> p <~ "}" }
def ir: Parser[IR] = rep(topLevel) ^^ IR
def topLevel: Parser[TopLevel] = typeDef | funcSigDef | constDef | globalDataDef | funcDecl | funcDef
def t = typeExpr
def s = funcSigExpr
def v = valueExpr
def l = lid
def g = gid
def typeDef: Parser[TypeDef] = ".typedef" ~> gid ~< "=" ~ typeCons ^^^^ TypeDef
def funcSigDef: Parser[FuncSigDef] = ".funcsig" ~> gid ~< "=" ~ funcSigCons ^^^^ FuncSigDef
def constDef: Parser[ConstDef] = ".const" ~> gid ~ ang(t) ~< "=" ~ constCons ^^^^ ConstDef
def globalDataDef: Parser[GlobalDataDef] = ".global" ~> gid ~ ang(t) ^^^^ GlobalDataDef
def funcDecl: Parser[FuncDecl] = ".funcdecl" ~> gid ~ ang(s) ^^^^ FuncDecl
def funcDef: Parser[FuncDef] = ".funcdef" ~> gid ~ ang(s) ~ paren(rep(l)) ~ funcBodyDef ^^^^ FuncDef
def typeExpr: Parser[TypeExpr] = gid ^^ ReferredType | typeCons
def typeCons: Parser[TypeCons] =
"int" ~> ang(intLit.asInt) ^^ IntCons |
"float" ^^^ FloatCons |
"double" ^^^ DoubleCons |
"ref" ~> ang(t) ^^ RefCons |
"iref" ~> ang(t) ^^ IRefCons |
"weakref" ~> ang(t) ^^ WeakRefCons |
"struct" ~> ang(rep(t)) ^^ StructCons |
"array" ~> ang(t ~ intLit.asLong) ^^^^ ArrayCons |
"hybrid" ~> ang(t ~ t) ^^^^ HybridCons |
"void" ^^^ VoidCons |
"func" ~> ang(s) ^^ FuncCons |
"thread" ^^^ ThreadCons |
"stack" ^^^ StackCons |
"tagref64" ^^^ TagRef64Cons
def funcSigExpr: Parser[FuncSigExpr] = funcSigCons | g ^^ ReferredFuncSig
def funcSigCons: Parser[FuncSigCons] = t ~ paren(rep(t)) ^^^^ FuncSigCons
def constExpr: Parser[ConstExpr] = g ^^ ReferredConst | constCons
def constCons: Parser[ConstCons] =
floatLit ^^ FloatConstCons |
doubleLit ^^ DoubleConstCons |
intLit ^^ IntConstCons |
brace(rep(constExpr)) ^^ StructConstCons |
"NULL" ^^^ NullConstCons
def funcBodyDef: Parser[FuncBodyDef] = brace(entryBlock ~ rep(regularBlock)) ^^^^ FuncBodyDef
def entryBlock: Parser[BasicBlockDef] = opt(label) ~ rep1(inst) ^^^^ BasicBlockDef
def regularBlock: Parser[BasicBlockDef] = (label ^^ { Some(_) }) ~ rep1(inst) ^^^^ BasicBlockDef
def label: Parser[LID] = l <~ ":"
def inst: Parser[InstDef] = opt(l <~ "=") ~ instCons ^^^^ InstDef
def instCons: Parser[InstCons] =
binOptr ~ ang(t) ~ v ~ v ^^^^ BinOpCons |
cmpOptr ~ ang(t) ~ v ~ v ^^^^ CmpCons |
convOptr ~ ang(t ~ t) ~ v ^^ { case a ~ (b ~ c) ~ d => ConvCons(a, b, c, d) } |
"SELECT" ~> ang(t) ~ v ~ v ~ v ^^^^ SelectCons |
"BRANCH" ~> l ^^ BranchCons |
"BRANCH2" ~> v ~ l ~ l ^^^^ Branch2Cons |
"SWITCH" ~> ang(t) ~ v ~ l ~ brace(vbMap) ^^^^ SwitchCons |
"PHI" ~> ang(t) ~ brace(bvMap) ^^^^ PhiCons |
"CALL" ~> ang(s) ~ v ~ args ~ maybeKeepAlive ^^^^ CallCons |
"INVOKE" ~> ang(s) ~ v ~ args ~ l ~ l ~ maybeKeepAlive ^^^^ InvokeCons |
"TAILCALL" ~> ang(s) ~ v ~ args ^^^^ TailCallCons |
"RET" ~> ang(t) ~ v ^^^^ RetCons |
"RETVOID" ^^^ RetVoidCons |
"THROW" ~> v ^^ ThrowCons |
"LANDINGPAD" ^^^ LandingpadCons |
"EXTRACTVALUE" ~> ang(t ~ intLit.asInt) ~ v ^^^^ ExtractValueCons |
"INSERTVALUE" ~> ang(t ~ intLit.asInt) ~ v ~ v ^^^^ InsertValueCons |
"NEW" ~> ang(t) ^^ NewCons |
"NEWHYBRID" ~> ang(t) ~ v ^^^^ NewHybridCons |
"ALLOCA" ~> ang(t) ^^ AllocaCons |
"ALLOCAHYBRID" ~> ang(t) ~ v ^^^^ AllocaHybridCons |
"GETIREF" ~> ang(t) ~ v ^^^^ GetIRefCons |
"GETFIELDIREF" ~> ang(t ~ intLit.asInt) ~ v ^^^^ GetFieldIRefCons |
"GETELEMIREF" ~> ang(t) ~ v ~ v ^^^^ GetElemIRefCons |
"SHIFTIREF" ~> ang(t) ~ v ~ v ^^^^ ShiftIRefCons |
"GETFIXEDPARTIREF" ~> ang(t) ~ v ^^^^ GetFixedPartIRefCons |
"GETVARPARTIREF" ~> ang(t) ~ v ^^^^ GetVarPartIRefCons |
"LOAD" ~> maybeMemOrd ~ ang(t) ~ v ^^^^ LoadCons |
"STORE" ~> maybeMemOrd ~ ang(t) ~ v ~ v ^^^^ StoreCons |
"CMPXCHG" ~> memOrd ~ memOrd ~ ang(t) ~ v ~ v ~ v ^^^^ CmpXchgCons |
"ATOMICRMW" ~> memOrd ~ atomicRMWOp ~ ang(t) ~ v ~ v ^^^^ AtomicRMWCons |
"FENCE" ~> memOrd ^^ FenceCons |
"TRAP" ~> ang(t) ~ l ~ l ~ keepAlive ^^^^ TrapCons |
"WATCHPOINT" ~> intLit.asInt ~ ang(t) ~ l ~ l ~ l ~ keepAlive ^^^^ WatchpointCons |
"CCALL" ~> callConv ~ ang(s) ~ v ~ args ^^^^ CCallCons |
"NEWSTACK" ~> ang(s) ~ v ~ args ^^^^ NewStackCons |
"ICALL" ~> g ~ args ~ maybeKeepAlive ^^^^ ICallCons |
"IINVOKE" ~> g ~ args ~ l ~ l ~ maybeKeepAlive ^^^^ IInvokeCons
def vbMap: Parser[Seq[(ValueExpr, LID)]] = rep(valueExpr ~< ":" ~ lid ~< ";" ^^ { case a ~ b => (a, b) })
def bvMap: Parser[Seq[(LID, ValueExpr)]] = rep(lid ~< ":" ~ valueExpr ~< ";" ^^ { case a ~ b => (a, b) })
def args: Parser[Seq[ValueExpr]] = paren(rep(v))
def keepAlive: Parser[Seq[LID]] = "KEEPALIVE" ~> paren(rep(l))
def maybeKeepAlive: Parser[Seq[LID]] = opt(keepAlive) ^^ { _.getOrElse(Nil) }
def valueExpr: Parser[ValueExpr] = id ^^ RefValue | constCons ^^ InlineValue
def binOptr: Parser[String] = "ADD|SUB|MUL|UDIV|SDIV|UREM|SREM|SHL|LSHR|ASHR|AND|OR|XOR|FADD|FSUB|FMUL|FDIV|FREM".r
def cmpOptr: Parser[String] = "EQ|NE|ULT|ULE|UGT|UGE|SLT|SLE|SGT|SGE|FTRUE|FFALSE|FEQ|FNE|FORD|FOEQ|FONE|FOLT|FOLE|FOGT|FOGE|FUNO|FUEQ|FUNE|FULT|FULE|FUGT|FUGE".r
def convOptr: Parser[String] = "TRUNC|ZEXT|SEXT|FPTRUNC|FPEXT|FPTOUI|FPTOSI|UITOFP|SITOFP|BITCAST|REFCAST|IREFCAST|FUNCCAST".r
def memOrd: Parser[String] = "NOT_ATOMIC|UNORDERED|MONOTONIC|ACQUIRE|RELEASE|ACQ_REL|SEQ_CST".r
def atomicRMWOp: Parser[String] = "XCHG|ADD|SUB|AND|NAND|OR|XOR|MIN|MAX|UMIN|UMAX".r
def callConv: Parser[String] = "DEFAULT".r
def maybeMemOrd: Parser[String] = opt(memOrd) ^^ { _.getOrElse("NOT_ATOMIC") }
def id: Parser[ID] = lid | gid
def lid: Parser[LID] = """%[a-zA-Z0-9-_.]+""".r ^^ LID
def gid: Parser[GID] = """@[a-zA-Z0-9-_.]+""".r ^^ GID
def sign: Parser[Boolean] = opt("+" ^^^ false | "-" ^^^ true) ^^ { _.getOrElse(false) }
def parseInt(radix: Int)(res: Boolean ~ String): BigInt = res match {
case neg ~ ns =>
val num = BigInt(ns, radix)
if (neg) -num else num
}
implicit class BigIntParserConv(p: Parser[BigInt]) {
def asInt: Parser[Int] = p ^^ { _.intValue }
def asLong: Parser[Long] = p ^^ { _.longValue }
}
def intLit: Parser[BigInt] =
sign ~< "0x" ~ """[0-9a-fA-F]+""".r ^^ parseInt(16) |
sign ~< "0" ~ """[0-9]+""".r ^^ parseInt(8) |
sign ~ """([1-9][0-9]*)|0""".r ^^ parseInt(10)
def floatLit: Parser[Float] =
"""[+-]?[0-9]+\.[0-9]+(e[+-]?[0-9]+)?""".r <~ "f" ^^ { _.toFloat } |
"nan" <~ "f" ^^^ Float.NaN |
"+inf" <~ "f" ^^^ Float.PositiveInfinity |
"-inf" <~ "f" ^^^ Float.NegativeInfinity |
"bitsf" ~> paren(intLit.asInt) ^^ { java.lang.Float.intBitsToFloat(_) }
def doubleLit: Parser[Double] =
"""[+-]?[0-9]+\.[0-9]+(e[+-]?[0-9]+)?""".r <~ "d" ^^ { _.toDouble } |
"nan" <~ "d" ^^^ Double.NaN |
"+inf" <~ "d" ^^^ Double.PositiveInfinity |
"-inf" <~ "d" ^^^ Double.NegativeInfinity |
"bitsd" ~> paren(intLit.asLong) ^^ { java.lang.Double.longBitsToDouble(_) }
def apply(input: java.lang.CharSequence): IR = handleNoSuccess(parseAll(ir, input))
def apply(input: java.io.Reader): IR = handleNoSuccess(parseAll(ir, input))
private def handleNoSuccess(pr: ParseResult[IR]): IR = pr match {
case Success(irNode, next) => irNode
case NoSuccess(msg, next) => throw new TextIRParsingException(
"line %d, col %d: %s".format(next.pos.line, next.pos.column, msg))
}
}
object UvmIRAST {
case class IR(topLevels: Seq[TopLevel])
abstract class TopLevel
case class TypeDef(name: GID, cons: TypeCons) extends TopLevel
abstract class TypeExpr
case class ReferredType(id: GID) extends TypeExpr
abstract class TypeCons extends TypeExpr
case class IntCons(length: Int) extends TypeCons
case object FloatCons extends TypeCons
case object DoubleCons extends TypeCons
case class RefCons(ty: TypeExpr) extends TypeCons
case class IRefCons(ty: TypeExpr) extends TypeCons
case class WeakRefCons(ty: TypeExpr) extends TypeCons
case class StructCons(fieldTy: Seq[TypeExpr]) extends TypeCons
case class ArrayCons(elemTy: TypeExpr, length: Long) extends TypeCons
case class HybridCons(fixedPart: TypeExpr, varPart: TypeExpr) extends TypeCons
case object VoidCons extends TypeCons
case class FuncCons(sig: FuncSigExpr) extends TypeCons
case object ThreadCons extends TypeCons
case object StackCons extends TypeCons
case object TagRef64Cons extends TypeCons
case class FuncSigDef(name: GID, cons: FuncSigCons) extends TopLevel
abstract class FuncSigExpr
case class ReferredFuncSig(id: GID) extends FuncSigExpr
case class FuncSigCons(retTy: TypeExpr, paramTy: Seq[TypeExpr]) extends FuncSigExpr
case class ConstDef(name: GID, ty: TypeExpr, cons: ConstCons) extends TopLevel
abstract class ConstExpr
case class ReferredConst(id: GID) extends ConstExpr
abstract class ConstCons extends ConstExpr
case class IntConstCons(num: BigInt) extends ConstCons
case class FloatConstCons(num: Float) extends ConstCons
case class DoubleConstCons(num: Double) extends ConstCons
case class StructConstCons(fields: Seq[ConstExpr]) extends ConstCons
case object NullConstCons extends ConstCons
case class GlobalDataDef(name: GID, ty: TypeExpr) extends TopLevel
case class FuncDecl(name: GID, sig: FuncSigExpr) extends TopLevel
case class FuncDef(name: GID, sig: FuncSigExpr, params: Seq[LID], body: FuncBodyDef) extends TopLevel
case class FuncBodyDef(entry: BasicBlockDef, bbs: Seq[BasicBlockDef])
case class BasicBlockDef(name: Option[LID], insts: Seq[InstDef])
case class InstDef(name: Option[LID], cons: InstCons)
abstract class InstCons
abstract class ValueExpr
case class RefValue(id: ID) extends ValueExpr
case class InlineValue(cons: ConstCons) extends ValueExpr
case class BinOpCons(op: String, opndTy: TypeExpr, op1: ValueExpr, op2: ValueExpr) extends InstCons
case class CmpCons(op: String, opndTy: TypeExpr, op1: ValueExpr, op2: ValueExpr) extends InstCons
case class ConvCons(op: String, fromTy: TypeExpr, toTy: TypeExpr, opnd: ValueExpr) extends InstCons
case class SelectCons(opndTy: TypeExpr, cond: ValueExpr, ifTrue: ValueExpr, ifFalse: ValueExpr) extends InstCons
case class BranchCons(dest: LID) extends InstCons
case class Branch2Cons(cond: ValueExpr, ifTrue: LID, ifFalse: LID) extends InstCons
case class SwitchCons(opndTy: TypeExpr, opnd: ValueExpr, defDest: LID, cases: Seq[(ValueExpr, LID)]) extends InstCons
case class PhiCons(opndTy: TypeExpr, cases: Seq[(LID, ValueExpr)]) extends InstCons
case class CallCons(sig: FuncSigExpr, callee: ValueExpr, args: Seq[ValueExpr], keepAlives: Seq[LID]) extends InstCons
case class InvokeCons(sig: FuncSigExpr, callee: ValueExpr, args: Seq[ValueExpr], nor: LID, exc: LID, keepAlives: Seq[LID]) extends InstCons
case class TailCallCons(sig: FuncSigExpr, callee: ValueExpr, args: Seq[ValueExpr]) extends InstCons
case class RetCons(retTy: TypeExpr, retVal: ValueExpr) extends InstCons
case object RetVoidCons extends InstCons
case class ThrowCons(excVal: ValueExpr) extends InstCons
case object LandingpadCons extends InstCons
case class ExtractValueCons(strTy: TypeExpr, index: Int, opnd: ValueExpr) extends InstCons
case class InsertValueCons(strTy: TypeExpr, index: Int, opnd: ValueExpr, newVal: ValueExpr) extends InstCons
case class NewCons(allocTy: TypeExpr) extends InstCons
case class NewHybridCons(allocTy: TypeExpr, length: ValueExpr) extends InstCons
case class AllocaCons(allocTy: TypeExpr) extends InstCons
case class AllocaHybridCons(allocTy: TypeExpr, length: ValueExpr) extends InstCons
case class GetIRefCons(referentTy: TypeExpr, opnd: ValueExpr) extends InstCons
case class GetFieldIRefCons(referentTy: TypeExpr, index: Int, opnd: ValueExpr) extends InstCons
case class GetElemIRefCons(referentTy: TypeExpr, opnd: ValueExpr, index: ValueExpr) extends InstCons
case class ShiftIRefCons(referentTy: TypeExpr, opnd: ValueExpr, offset: ValueExpr) extends InstCons
case class GetFixedPartIRefCons(referentTy: TypeExpr, opnd: ValueExpr) extends InstCons
case class GetVarPartIRefCons(referentTy: TypeExpr, opnd: ValueExpr) extends InstCons
case class LoadCons(ord: String, referentTy: TypeExpr, loc: ValueExpr) extends InstCons
case class StoreCons(ord: String, referentTy: TypeExpr, loc: ValueExpr, newVal: ValueExpr) extends InstCons
case class CmpXchgCons(ordSucc: String, ordFail: String, referentTy: TypeExpr,
loc: ValueExpr, expected: ValueExpr, desired: ValueExpr) extends InstCons
case class AtomicRMWCons(ord: String, op: String, referentTy: TypeExpr, loc: ValueExpr, newVal: ValueExpr) extends InstCons
case class FenceCons(ord: String) extends InstCons
case class TrapCons(retTy: TypeExpr, nor: LID, exc: LID, keepAlives: Seq[LID]) extends InstCons
case class WatchpointCons(wpID: Int, retTy: TypeExpr, dis: LID, nor: LID, exc: LID, keepAlives: Seq[LID]) extends InstCons
case class CCallCons(callConv: String, sig: FuncSigExpr, callee: ValueExpr, args: Seq[ValueExpr]) extends InstCons
case class NewStackCons(sig: FuncSigExpr, callee: ValueExpr, args: Seq[ValueExpr]) extends InstCons
case class ICallCons(iFunc: GID, args: Seq[ValueExpr], keepAlives: Seq[LID]) extends InstCons
case class IInvokeCons(iFunc: GID, args: Seq[ValueExpr], nor: LID, exc: LID, keepAlives: Seq[LID]) extends InstCons
abstract class ID(name: String)
case class GID(name: String) extends ID(name)
case class LID(name: String) extends ID(name)
case class IntLit(num: BigInt)
case class FloatLit(num: Float)
case class DoubleLit(num: Double)
case object NullLit
}
\ No newline at end of file
package uvm.ir.textinput
import uvm._
import uvm.types._
import uvm.ssavalues._
import uvm.ifuncs._
object UvmIRReader {
import UvmIRAST._
import Later.Laterable
def read(ir: CharSequence, globalBundle: Bundle): Bundle = {
val ast = UvmIRParser(ir)
read(ast, globalBundle)
}
def read(ir: java.io.Reader, globalBundle: Bundle): Bundle = {
val ast = UvmIRParser(ir)
read(ast, globalBundle)
}
object IDFactory {
private var id: Int = 65536
def getID(): Int = {
val myID = id
id = id + 1
return myID
}
}
def read(ir: IR, globalBundle: Bundle): Bundle = {
val bundle = new Bundle()
val phase1 = new Later()
def resTy(te: TypeExpr): Type = te match {
case ReferredType(g) => bundle.typeNs.get(g.name).getOrElse(globalBundle.typeNs(g.name))
case tc: TypeCons => mkType(tc)
}
def mkType(tc: TypeCons): Type = {
val ty = tc match {
case IntCons(l) => TypeInt(l)
case FloatCons => TypeFloat()
case DoubleCons => TypeDouble()
case RefCons(t) => TypeRef(null).later(phase1) { _.ty = resTy(t) }
case IRefCons(t) => TypeIRef(null).later(phase1) { _.ty = resTy(t) }
case WeakRefCons(t) => TypeWeakRef(null).later(phase1) { _.ty = resTy(t) }
case StructCons(fs) => TypeStruct(null).later(phase1) { _.fieldTy = fs.map(resTy) }
case ArrayCons(et, l) => TypeArray(null, l).later(phase1) { _.elemTy = resTy(et) }
case HybridCons(fp, vp) => TypeHybrid(null, null).later(phase1) { h => h.fixedPart = resTy(fp); h.varPart = resTy(vp) }
case VoidCons => TypeVoid()
case FuncCons(s) => TypeFunc(null).later(phase1) { _.sig = resSig(s) }
case ThreadCons => TypeThread()
case StackCons => TypeStack()
case TagRef64Cons => TypeTagRef64()
case _ => throw new RuntimeException("foo")
}
ty.id = IDFactory.getID()
return ty
}
def resSig(se: FuncSigExpr): FuncSig = se match {
case ReferredFuncSig(g) => bundle.funcSigNs.get(g.name).getOrElse(globalBundle.funcSigNs(g.name))
case FuncSigCons(r, ps) => mkSig(r, ps)
}
def mkSig(r: TypeExpr, ps: Seq[TypeExpr]): FuncSig = {
val sig = FuncSig(null, null).later(phase1) { sig =>
sig.retTy = resTy(r)
sig.paramTy = ps.map(resTy)
}
sig.id = IDFactory.getID()
return sig
}
ir.topLevels.foreach {
case TypeDef(n, c) => {
val ty = mkType(c)
ty.name = Some(n.name)
bundle.typeNs.add(ty)
}
case FuncSigDef(n, FuncSigCons(r, ps)) => {
val sig = mkSig(r, ps)
sig.name = Some(n.name)
bundle.funcSigNs.add(sig)
}
case _ => {}
}
phase1.doAll()