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Commit 4d4846eb authored by Kunshan Wang's avatar Kunshan Wang

Testing instructions...

parent 4a47a86d
......@@ -26,6 +26,8 @@ class FuncVer extends IdentifiedSettable {
val bbNs: Namespace[BasicBlock] = new SimpleNamespace[BasicBlock]()
val localVarNs: Namespace[LocalVariable] = new SimpleNamespace[LocalVariable]()
def sig: FuncSig = func.sig
}
class BasicBlock extends IdentifiedSettable {
......
......@@ -65,7 +65,7 @@ class UIRTextReader(val idFactory: IDFactory) {
val neg = sign match {
case "+" => false
case "-" => true
case "" => true
case "" => false
}
val abs = prefix match {
case "0x" => BigInt(nums, 16)
......@@ -310,7 +310,7 @@ class UIRTextReader(val idFactory: IDFactory) {
ver.func = func
func.versions = ver :: func.versions
def globalize(name: String): String = if (name(0) == '@') name else (ver.name.get + "." + name.substring(1))
def globalize(name: String): String = UIRTextReader.globalize(name, ver.name.get)
ver.params = fDefCtx.params.name().zipWithIndex.map {
case (n, i) =>
......@@ -477,7 +477,7 @@ class UIRTextReader(val idFactory: IDFactory) {
i.excClause = ii.excClause
}
case ii: InstNewHybridContext =>
InstNewHybrid(needHybrid(ii.allocTy), null, null).later(phase4) { i =>
InstNewHybrid(needHybrid(ii.allocTy), needInt(ii.lenTy), null, null).later(phase4) { i =>
i.length = ii.length; i.excClause = ii.excClause
}
case ii: InstAllocaContext =>
......@@ -485,48 +485,52 @@ class UIRTextReader(val idFactory: IDFactory) {
i.excClause = ii.excClause
}
case ii: InstAllocaHybridContext =>
InstAllocaHybrid(needHybrid(ii.allocTy), null, null).later(phase4) { i =>
InstAllocaHybrid(needHybrid(ii.allocTy), needInt(ii.lenTy), null, null).later(phase4) { i =>
i.length = ii.length; i.excClause = ii.excClause
}
case ii: InstGetIRefContext =>
InstGetIRef(ii.refTy, null).later(phase4) { i =>
i.opnd = i.opnd
i.opnd = ii.opnd
}
case ii: InstGetFieldIRefContext =>
InstGetFieldIRef(needStruct(ii.refTy), ii.intLiteral.intValue, null).later(phase4) { i =>
i.opnd = i.opnd
i.opnd = ii.opnd
}
case ii: InstGetElemIRefContext =>
InstGetElemIRef(needSeq(ii.refTy), needInt(ii.indTy), null, null).later(phase4) { i =>
i.opnd = i.opnd; i.index = ii.index
i.opnd = ii.opnd; i.index = ii.index
}
case ii: InstShiftIRefContext =>
InstShiftIRef(ii.refTy, needInt(ii.offTy), null, null).later(phase4) { i =>
i.opnd = i.opnd; i.offset = ii.offset
i.opnd = ii.opnd; i.offset = ii.offset
}
case ii: InstGetFixedPartIRefContext =>
InstGetFixedPartIRef(needHybrid(ii.refTy), null).later(phase4) { i =>
i.opnd = i.opnd
i.opnd = ii.opnd
}
case ii: InstGetVarPartIRefContext =>
InstGetVarPartIRef(needHybrid(ii.refTy), null).later(phase4) { i =>
i.opnd = i.opnd
i.opnd = ii.opnd
}
case ii: InstLoadContext =>
InstLoad(ii.memord, ii.`type`, null).later(phase4) { i =>
InstLoad(ii.memord, ii.`type`, null, null).later(phase4) { i =>
i.loc = ii.loc
i.excClause = ii.excClause
}
case ii: InstStoreContext =>
InstStore(ii.memord, ii.`type`, null, null).later(phase4) { i =>
InstStore(ii.memord, ii.`type`, null, null, null).later(phase4) { i =>
i.loc = ii.loc; i.newVal = ii.newVal
i.excClause = ii.excClause
}
case ii: InstCmpXchgContext =>
InstCmpXchg(ii.isWeak != null, ii.ordSucc, ii.ordFail, ii.`type`, null, null, null).later(phase4) { i =>
InstCmpXchg(ii.isWeak != null, ii.ordSucc, ii.ordFail, ii.`type`, null, null, null, null).later(phase4) { i =>
i.loc = ii.loc; i.expected = ii.expected; i.desired = ii.desired
i.excClause = ii.excClause
}
case ii: InstAtomicRMWContext =>
InstAtomicRMW(ii.memord, AtomicRMWOptr.withName(ii.atomicrmwop.getText), ii.`type`, null, null).later(phase4) { i =>
InstAtomicRMW(ii.memord, AtomicRMWOptr.withName(ii.atomicrmwop.getText), ii.`type`, null, null, null).later(phase4) { i =>
i.loc = ii.loc; i.opnd = ii.opnd
i.excClause = ii.excClause
}
case ii: InstFenceContext =>
InstFence(ii.memord)
......@@ -591,4 +595,15 @@ class UIRTextReader(val idFactory: IDFactory) {
return bundle
}
}
object UIRTextReader {
def globalize(name: String, fvName: String): String = {
val sigil = name.charAt(0)
sigil match {
case '@' => name
case '%' => fvName + "." + name.substring(1)
case _ => throw new UvmException("Illegal name '%s'. Name must begin with either '@' or '%%'".format(name))
}
}
}
\ No newline at end of file
......@@ -121,6 +121,7 @@ abstract class AbstractAlloc extends HasExcClause {
trait FixedAlloc extends AbstractAlloc
trait HybridAlloc extends AbstractAlloc {
def lenTy: TypeInt
def length: SSAVariable
}
......@@ -191,11 +192,11 @@ case class InstShuffleVector(var vecTy: TypeVector, var maskTy: TypeVector,
case class InstNew(var allocTy: Type, var excClause: Option[ExcClause]) extends HeapAlloc with FixedAlloc
case class InstNewHybrid(var allocTy: TypeHybrid, var length: SSAVariable, var excClause: Option[ExcClause]) extends HeapAlloc with HybridAlloc
case class InstNewHybrid(var allocTy: TypeHybrid, var lenTy: TypeInt, var length: SSAVariable, var excClause: Option[ExcClause]) extends HeapAlloc with HybridAlloc
case class InstAlloca(var allocTy: Type, var excClause: Option[ExcClause]) extends StackAlloc with FixedAlloc
case class InstAllocaHybrid(var allocTy: TypeHybrid, var length: SSAVariable, var excClause: Option[ExcClause]) extends StackAlloc with HybridAlloc
case class InstAllocaHybrid(var allocTy: TypeHybrid, var lenTy: TypeInt, var length: SSAVariable, var excClause: Option[ExcClause]) extends StackAlloc with HybridAlloc
case class InstGetIRef(var referentTy: Type, var opnd: SSAVariable) extends Instruction
......@@ -211,17 +212,17 @@ case class InstGetFixedPartIRef(var referentTy: TypeHybrid, var opnd: SSAVariabl
case class InstGetVarPartIRef(var referentTy: TypeHybrid, var opnd: SSAVariable) extends Instruction
case class InstLoad(var ord: MemoryOrder, var referentTy: Type, var loc: SSAVariable) extends Instruction
case class InstLoad(var ord: MemoryOrder, var referentTy: Type, var loc: SSAVariable, var excClause: Option[ExcClause]) extends HasExcClause
case class InstStore(var ord: MemoryOrder, var referentTy: Type, var loc: SSAVariable, var newVal: SSAVariable) extends Instruction
case class InstStore(var ord: MemoryOrder, var referentTy: Type, var loc: SSAVariable, var newVal: SSAVariable, var excClause: Option[ExcClause]) extends HasExcClause
case class InstCmpXchg(var weak: Boolean, var ordSucc: MemoryOrder, var ordFail: MemoryOrder, var referentTy: Type,
var loc: SSAVariable, var expected: SSAVariable, var desired: SSAVariable) extends Instruction
case class InstFence(var ord: MemoryOrder) extends Instruction
var loc: SSAVariable, var expected: SSAVariable, var desired: SSAVariable, var excClause: Option[ExcClause]) extends HasExcClause
case class InstAtomicRMW(var ord: MemoryOrder, var op: AtomicRMWOptr,
var referentTy: Type, var loc: SSAVariable, var opnd: SSAVariable) extends Instruction
var referentTy: Type, var loc: SSAVariable, var opnd: SSAVariable, var excClause: Option[ExcClause]) extends HasExcClause
case class InstFence(var ord: MemoryOrder) extends Instruction
case class InstTrap(var retTy: Type, var excClause: Option[ExcClause], var keepAlives: Seq[LocalVariable]) extends AbstractTrap
......
......@@ -3,11 +3,11 @@ package uvm.ir.textinput
import org.scalatest._
import uvm._
trait AbstractReaderSpec extends FlatSpec with Matchers {
// with TestingBundlesValidators {
trait AbstractReaderSpec extends FlatSpec with Matchers
with TestingBundlesValidators {
val EMPTY_BUNDLE = new Bundle()
def parseFile(fileName: String, globalBundle: Bundle): Bundle
def theSubject: String
......@@ -16,25 +16,25 @@ trait AbstractReaderSpec extends FlatSpec with Matchers {
it should "read simple type definitions" in {
val b = parseFile("tests/uvm-parsing-test/types.uir", EMPTY_BUNDLE)
//validateTypes(b)
validateTypes(b)
}
it should "read simple constant definitions" in {
val b = parseFile("tests/uvm-parsing-test/constants.uir", EMPTY_BUNDLE)
//validateConstants(b)
validateConstants(b)
}
it should "read simple function definitions" in {
val b = parseFile("tests/uvm-parsing-test/functions.uir", EMPTY_BUNDLE)
//validateFunctions(b)
validateFunctions(b)
}
it should "read simple instruction definitions" in {
val b = parseFile("tests/uvm-parsing-test/instructions.uir", EMPTY_BUNDLE)
//validateInstructions(b)
validateInstructions(b)
}
it should "handle loading of multiple bundles" in {
//val gb = parseFile("tests/uvm-parsing-test/redef-base.uir", EMPTY_BUNDLE)
//val b = parseFile("tests/uvm-parsing-test/redef-overlay.uir", gb)
//validateRedef(gb, b)
//gb.merge(b)
//validateRedefAfterMerge(gb, b)
}
......
......@@ -70,18 +70,10 @@
.const @I32_4 <@float> = 4
.const @D_1 <@float> = 1.0d
.const @D_2 <@float> = 2.0d
.const @D_3 <@float> = 3.0d
.const @D_4 <@float> = 4.0d
.const @cv4f <@4xfloat> = VEC {@F_1 @F_2 @F_3 @F_4}
.const @cv4i <@4xi32> = VEC {@I32_1 @I32_2 @I32_3 @I32_4}
.const @cv4d <@2xdouble> = VEC {@D_1 @D_2 @D_3 @D_4}
.typedef @Cons = struct<@i32 @RefCons>
.typedef @RefCons = ref<@Cons>
.const @cons0 <@Cons> = {@ci32 @consNull}
.const @consNull <@RefCons> = NULL
.const @cv4d <@2xdouble> = VEC {@D_1 @D_2}
.global @gi64 <@i64>
.funcdecl @fdummy <@sig0>
......
......@@ -246,7 +246,7 @@
%i1 = INSERTVALUE <@sid 1> @sid1 @D_0
%ee0 = EXTRACTELEMENT <@4xfloat @i32> @v1 @I32_0
%ie0 = INSERTELEMENT <@4xfloat @i32> @v1 @I32_1 @F_1
%fv0 = SHUFFLEVECTOR <@4xfloat @4xi32> @v1 @v2 @vshf
%sv0 = SHUFFLEVECTOR <@4xfloat @4xi32> @v1 @v2 @vshf
RETVOID
}
......
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