Commit ba938c48 authored by Kunshan Wang's avatar Kunshan Wang

Fixed IRBuilder COMMINST bugs

- Implemented @uvm.irbuilder.new_ir_builder

- Fixed @uvm.irbuilder.gen_sym where the %name parameter should be optional
parent d8d384ea
...@@ -326,8 +326,14 @@ def gen_comminst_impl(comminst): ...@@ -326,8 +326,14 @@ def gen_comminst_impl(comminst):
lines.append(' val {} = {} != 0'.format(bool_name, cname)) lines.append(' val {} = {} != 0'.format(bool_name, cname))
ir_builder_args.append(bool_name) ir_builder_args.append(bool_name)
elif cty in ["MuName", "MuCString"]: elif cty in ["MuName", "MuCString"]:
str_name = "_str_" + cname
lines.append(' val {} = loadCString({})'.format(str_name, cname)) if cname in comminst.optionals:
str_name = "_maybestr_" + cname
lines.append(' val {} = loadMaybeCString({})'.format(str_name, cname))
else:
str_name = "_str_" + cname
lines.append(' val {} = loadCString({})'.format(str_name, cname))
ir_builder_args.append(str_name) ir_builder_args.append(str_name)
else: else:
ir_builder_args.append(cname) ir_builder_args.append(cname)
......
...@@ -64,6 +64,8 @@ object CommInsts extends SimpleNamespace[CommInst] { ...@@ -64,6 +64,8 @@ object CommInsts extends SimpleNamespace[CommInst] {
commInst(0x25f, "@uvm.meta.disable_watchPoint") commInst(0x25f, "@uvm.meta.disable_watchPoint")
commInst(0x260, "@uvm.meta.set_trap_handler") commInst(0x260, "@uvm.meta.set_trap_handler")
commInst(0x270, "@uvm.irbuilder.new_ir_builder")
// Proprietary extensions specific to this refimpl // Proprietary extensions specific to this refimpl
commInst(0xc001, "@uvm.ext.print_stats") commInst(0xc001, "@uvm.ext.print_stats")
......
...@@ -196,6 +196,8 @@ object TypeInferer { ...@@ -196,6 +196,8 @@ object TypeInferer {
case "@uvm.meta.disable_watchPoint" => Seq() case "@uvm.meta.disable_watchPoint" => Seq()
case "@uvm.meta.set_trap_handler" => Seq() case "@uvm.meta.set_trap_handler" => Seq()
case "@uvm.irbuilder.new_ir_builder" => Seq(IRBUILDERREF)
/// GEN:BEGIN:IRBUILDER_RETVALS /// GEN:BEGIN:IRBUILDER_RETVALS
case "@uvm.irbuilder.load" => Seq() case "@uvm.irbuilder.load" => Seq()
......
...@@ -22,11 +22,11 @@ object IRBuilderCommInstExecutor { ...@@ -22,11 +22,11 @@ object IRBuilderCommInstExecutor {
implicit def toCommInst(i: Int): CommInst = CommInsts(i) implicit def toCommInst(i: Int): CommInst = CommInsts(i)
def unsignedLongSeqToBigInt(nums: Seq[Long]): BigInt = { def unsignedLongSeqToBigInt(nums: Seq[Long]): BigInt = {
var bigNum = BigInt(0) var bigNum = BigInt(0)
for (num <- nums) { for (num <- nums) {
bigNum = (bigNum << 64) | (BigInt(num) & 0xffffffffffffffffL) bigNum = (bigNum << 64) | (BigInt(num) & 0xffffffffffffffffL)
} }
bigNum bigNum
} }
implicit class IDOptionalUtil(val id: MuID) extends AnyVal { implicit class IDOptionalUtil(val id: MuID) extends AnyVal {
def asOptionalID: Option[MuID] = if (id == 0) None else Some(id) def asOptionalID: Option[MuID] = if (id == 0) None else Some(id)
...@@ -41,40 +41,57 @@ trait IRBuilderCommInstExecutor extends InterpreterActions with ObjectPinner { ...@@ -41,40 +41,57 @@ trait IRBuilderCommInstExecutor extends InterpreterActions with ObjectPinner {
implicit protected def mutator: Mutator implicit protected def mutator: Mutator
implicit protected def memorySupport: MemorySupport implicit protected def memorySupport: MemorySupport
protected def loadInt64Array(ir: (Word, Word), sz: Word): IndexedSeq[Long] = { protected def loadInt64Array(ir: (Word, Word), sz: Word): IndexedSeq[Long] = {
val (obj,off) = ir val (obj, off) = ir
val loc = obj + off val loc = obj + off
MemoryOperations.loadInt64Array(loc, sz) MemoryOperations.loadInt64Array(loc, sz)
} }
protected def loadInt32Array(ir: (Word, Word), sz: Word): IndexedSeq[Int] = { protected def loadInt32Array(ir: (Word, Word), sz: Word): IndexedSeq[Int] = {
val (obj,off) = ir val (obj, off) = ir
val loc = obj + off val loc = obj + off
MemoryOperations.loadInt32Array(loc, sz) MemoryOperations.loadInt32Array(loc, sz)
} }
protected def loadFlagArray(ir: (Word, Word), sz: Word): IndexedSeq[Flag] = { protected def loadFlagArray(ir: (Word, Word), sz: Word): IndexedSeq[Flag] = {
val (obj,off) = ir val (obj, off) = ir
val loc = obj + off val loc = obj + off
MemoryOperations.loadInt32Array(loc, sz).map(toFlag) MemoryOperations.loadInt32Array(loc, sz).map(toFlag)
} }
protected def loadCString(ir: (Word, Word)): String = { protected def loadCString(ir: (Word, Word)): String = {
val (obj,off) = ir val (obj, off) = ir
val loc = obj + off val loc = obj + off
MemoryOperations.bytesToStr(loc) MemoryOperations.bytesToStr(loc)
} }
protected def loadMaybeCString(ir: (Word, Word)): Option[String] = {
val (obj, off) = ir
val loc = obj + off
loc match {
case 0L => None
case _ => Some(MemoryOperations.bytesToStr(loc))
}
}
private type TB = TrantientBundle private type TB = TrantientBundle
def interpretCurrentIRBuilderCommonInstruction(): Unit = { def interpretCurrentIRBuilderCommonInstruction(): Unit = {
assert(curInst.isInstanceOf[InstCommInst]) assert(curInst.isInstanceOf[InstCommInst])
val InstCommInst(ci, _, _, _, argList, _, _) = curInst val InstCommInst(ci, _, _, _, argList, _, _) = curInst
assert(ci.name.get.startsWith("@uvm.irbuilder")) assert(ci.name.get.startsWith("@uvm.irbuilder"))
ci.name.get match { ci.name.get match {
case "@uvm.irbuilder.new_ir_builder" => {
val irBuilder = microVM.newIRBuilder()
results(0).asIRBuilder = Some(irBuilder)
continueNormally()
}
/// The auto-generated implementations work just fine. /// The auto-generated implementations work just fine.
//case "@uvm.irbuilder.load" => { //case "@uvm.irbuilder.load" => {
// val _param0 = argList(0).asIRBuilder.get // val _param0 = argList(0).asIRBuilder.get
...@@ -86,7 +103,7 @@ trait IRBuilderCommInstExecutor extends InterpreterActions with ObjectPinner { ...@@ -86,7 +103,7 @@ trait IRBuilderCommInstExecutor extends InterpreterActions with ObjectPinner {
// _param0.abort() // _param0.abort()
// continueNormally() // continueNormally()
//} //}
// Auto-generated implementations go here // Auto-generated implementations go here
/// GEN:BEGIN:IRBUILDER_IMPL /// GEN:BEGIN:IRBUILDER_IMPL
case "@uvm.irbuilder.load" => { case "@uvm.irbuilder.load" => {
...@@ -102,8 +119,8 @@ trait IRBuilderCommInstExecutor extends InterpreterActions with ObjectPinner { ...@@ -102,8 +119,8 @@ trait IRBuilderCommInstExecutor extends InterpreterActions with ObjectPinner {
case "@uvm.irbuilder.gen_sym" => { case "@uvm.irbuilder.gen_sym" => {
val b = argList(0).asIRBuilder.getOrElse(throw new UvmNullGenRefException("CommInst arg %b must not be null")) val b = argList(0).asIRBuilder.getOrElse(throw new UvmNullGenRefException("CommInst arg %b must not be null"))
val name = argList(1).asIRef val name = argList(1).asIRef
val _str_name = loadCString(name) val _maybestr_name = loadMaybeCString(name)
val _rv = b.genSym(_str_name) val _rv = b.genSym(_maybestr_name)
results(0).asInt32 = _rv results(0).asInt32 = _rv
continueNormally() continueNormally()
} }
...@@ -750,12 +767,12 @@ trait IRBuilderCommInstExecutor extends InterpreterActions with ObjectPinner { ...@@ -750,12 +767,12 @@ trait IRBuilderCommInstExecutor extends InterpreterActions with ObjectPinner {
val is_ptr = argList(3).asInt32.toInt val is_ptr = argList(3).asInt32.toInt
val ord = argList(4).asInt32.toInt val ord = argList(4).asInt32.toInt
val optr = argList(5).asInt32.toInt val optr = argList(5).asInt32.toInt
val refTy = argList(6).asInt32.toInt val ref_ty = argList(6).asInt32.toInt
val loc = argList(7).asInt32.toInt val loc = argList(7).asInt32.toInt
val opnd = argList(8).asInt32.toInt val opnd = argList(8).asInt32.toInt
val exc_clause = argList(9).asInt32.toInt.asOptionalID val exc_clause = argList(9).asInt32.toInt.asOptionalID
val _bool_is_ptr = is_ptr != 0 val _bool_is_ptr = is_ptr != 0
val _rv = b.newAtomicRMW(id, result_id, _bool_is_ptr, ord, optr, refTy, loc, opnd, exc_clause) val _rv = b.newAtomicRMW(id, result_id, _bool_is_ptr, ord, optr, ref_ty, loc, opnd, exc_clause)
continueNormally() continueNormally()
} }
case "@uvm.irbuilder.new_fence" => { case "@uvm.irbuilder.new_fence" => {
......
package uvm.refimpl.itpr
import org.scalatest._
import java.io.FileReader
import uvm._
import uvm.types._
import uvm.ssavariables._
import uvm.refimpl._
import uvm.refimpl.itpr._
import MemoryOrder._
import AtomicRMWOptr._
import uvm.refimpl.Word
import ch.qos.logback.classic.Level._
import uvm.refimpl.UvmBundleTesterBase
import uvm.refimpl.TrapHandlerResult.{ ThreadExit, Rebind }
import uvm.refimpl.HowToResume.{ PassValues, ThrowExc }
import uvm.ir.irbuilder.IRBuilder
import uvm.ir.textinput.ExtraMatchers
class UvmInterpreterIRBuilderTests extends UvmBundleTesterBase with ExtraMatchers {
setLogLevels(
ROOT_LOGGER_NAME -> INFO,
"uvm.refimpl.itpr" -> DEBUG)
preloadBundles("tests/uvm-refimpl-test/primitives.uir",
"tests/uvm-refimpl-test/irbuilder-tests.uir")
"The new_ir_builder COMMINST" should "create an IR builder" in {
val ctx = microVM.newContext()
val func = ctx.handleFromFunc("@irbuilder_test")
testFunc(ctx, func, Seq()) { (ctx, th, st, wp) =>
val trapName = nameOf(ctx.curInst(st, 0))
trapName match {
case "@irbuilder_test.v1.entry.trap" => {
val Seq(irb: MuOpaqueRefValue[IRBuilder], id1: MuIntValue) = ctx.dumpKeepalives(st, 0)
irb.vb.obj.get shouldBeA[IRBuilder] thatsIt
(id1.asInt32 >= 65536) shouldBe true
returnFromTrap(st)
}
case _ => fail("Should not hit " + trapName)
}
}
ctx.closeContext()
}
}
\ No newline at end of file
.const @NULLIREFI8 <@irefi8> = NULL
.funcdef @irbuilder_test VERSION %v1 <@v_v> {
%entry():
%irb = COMMINST @uvm.irbuilder.new_ir_builder
%id1 = COMMINST @uvm.irbuilder.gen_sym (%irb @NULLIREFI8)
[%trap] TRAP <> KEEPALIVE (%irb %id1)
COMMINST @uvm.irbuilder.load(%irb)
COMMINST @uvm.thread_exit
}
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