Commit bc578970 authored by Kunshan Wang's avatar Kunshan Wang

Automagic reloc configurable by option

Now "automagic relocation" can be enabled by a VMConf option
"automagicReloc".  It is disabled by default.
parent e701e3d5
...@@ -199,6 +199,11 @@ globalSize must be a multiple of 32768 bytes (32K).* ...@@ -199,6 +199,11 @@ globalSize must be a multiple of 32768 bytes (32K).*
- **sourceInfo**: Provide line/column info in Mu IR when errors occur. May be - **sourceInfo**: Provide line/column info in Mu IR when errors occur. May be
useful for debugging small Mu IR bundles, but will significantly slow down useful for debugging small Mu IR bundles, but will significantly slow down
parsing!!! Enable only if the bundle is small. default: false parsing!!! Enable only if the bundle is small. default: false
- **automagicReloc**: Allow "automagic" relocation. If true, `uptr` and
`ufuncptr` fields will also be traced during boot image building. If a `uptr`
field points to a global cell field, it will still point to the same field
after boot image loading; if a `ufuncptr` points to a native function, it will
point to the same function after boot image loading. default: false
- **extraLibs**: Extra libraries to load when starting the micro VM. This is a - **extraLibs**: Extra libraries to load when starting the micro VM. This is a
colon-separated list of libraries. Each library has the same syntax of the colon-separated list of libraries. Each library has the same syntax of the
`path` argument of the `dlopen` system function. By default, it does not load `path` argument of the `dlopen` system function. By default, it does not load
......
...@@ -106,6 +106,12 @@ object VMConfParser { ...@@ -106,6 +106,12 @@ object VMConfParser {
parser = parseBoolean, parser = parseBoolean,
default = VMConf.DEFAULT_CONF.sourceInfo) default = VMConf.DEFAULT_CONF.sourceInfo)
val automagicReloc = opt[Boolean](
name = "automagicReloc",
desc = """'Automagic' relocation. Affects boot image building, but not loading.""",
parser = parseBoolean,
default = VMConf.DEFAULT_CONF.automagicReloc)
val extraLibs = opt[Seq[String]]( val extraLibs = opt[Seq[String]](
name = "extraLibs", name = "extraLibs",
desc = """Extra libraries to load when starting the micro VM. This is a colon-separated list of libraries. desc = """Extra libraries to load when starting the micro VM. This is a colon-separated list of libraries.
...@@ -163,6 +169,7 @@ object VMConf { ...@@ -163,6 +169,7 @@ object VMConf {
dumpBundle = VMConfParser.dumpBundle(kvMap), dumpBundle = VMConfParser.dumpBundle(kvMap),
staticCheck = VMConfParser.staticCheck(kvMap), staticCheck = VMConfParser.staticCheck(kvMap),
sourceInfo = VMConfParser.sourceInfo(kvMap), sourceInfo = VMConfParser.sourceInfo(kvMap),
automagicReloc = VMConfParser.automagicReloc(kvMap),
extraLibs = VMConfParser.extraLibs(kvMap), extraLibs = VMConfParser.extraLibs(kvMap),
bootImg = VMConfParser.bootImg(kvMap) bootImg = VMConfParser.bootImg(kvMap)
) )
...@@ -187,6 +194,7 @@ class VMConf( ...@@ -187,6 +194,7 @@ class VMConf(
val dumpBundle: Boolean = false, val dumpBundle: Boolean = false,
val staticCheck: Boolean = true, val staticCheck: Boolean = true,
val sourceInfo: Boolean = false, val sourceInfo: Boolean = false,
val automagicReloc: Boolean = false,
val extraLibs: Seq[String] = Seq(), val extraLibs: Seq[String] = Seq(),
val bootImg: Option[String] = None) val bootImg: Option[String] = None)
...@@ -74,6 +74,8 @@ class BootImageWriter(tcb: TransitiveClosureBuilder, syms: Seq[FieldAndSymbol], ...@@ -74,6 +74,8 @@ class BootImageWriter(tcb: TransitiveClosureBuilder, syms: Seq[FieldAndSymbol],
import BootImageWriter._ import BootImageWriter._
import BootImageFile._ import BootImageFile._
val automagicReloc = microVM.vmConf.automagicReloc
val bundleSerializer = new BundleSerializer(microVM.globalBundle, tcb.tls.set) val bundleSerializer = new BundleSerializer(microVM.globalBundle, tcb.tls.set)
val tempDir = Files.createTempDirectory("mu-bootimg") val tempDir = Files.createTempDirectory("mu-bootimg")
...@@ -227,30 +229,34 @@ class BootImageWriter(tcb: TransitiveClosureBuilder, syms: Seq[FieldAndSymbol], ...@@ -227,30 +229,34 @@ class BootImageWriter(tcb: TransitiveClosureBuilder, syms: Seq[FieldAndSymbol],
logger.debug("External uptr relocation: %d 0x%x -> %s".format(iRef, iRef, symbol)) logger.debug("External uptr relocation: %d 0x%x -> %s".format(iRef, iRef, symbol))
} }
case None => { case None => {
// maybe a "reasonable" pointer to a mu global cell. Relocate it too. if (automagicReloc) {
val fieldOffset = iRef - objRef // maybe a "reasonable" pointer to a mu global cell. Relocate it too.
val maybeGlobalCell = tcb.maybeGetGlobalCellRec(toAddr) val fieldOffset = iRef - objRef
maybeGlobalCell match { val maybeGlobalCell = tcb.maybeGetGlobalCellRec(toAddr)
case Some(gcr) => maybeGlobalCell match {
val targetNum = gcr.g.id.toLong case Some(gcr) =>
val targetAddr = gcr.begin val targetNum = gcr.g.id.toLong
val targetOffset = toAddr - targetAddr val targetAddr = gcr.begin
val reloc = FieldRelocRecord(num, fieldOffset, AS_UPTR, TO_GLOBAL, targetNum, targetOffset, NO_SYM) val targetOffset = toAddr - targetAddr
group.relocRecs += reloc val reloc = FieldRelocRecord(num, fieldOffset, AS_UPTR, TO_GLOBAL, targetNum, targetOffset, NO_SYM)
logger.info("Relocation entry for uptr field automatically generated: %d 0x%x -> %d 0x%x".format( group.relocRecs += reloc
iRef, iRef, toAddr, toAddr)) logger.info("Relocation entry for uptr field automatically generated: %d 0x%x -> %d 0x%x".format(
case None => iRef, iRef, toAddr, toAddr))
case None =>
}
} }
} }
} }
} }
def visitUFPField(objRef: Word, iRef: Word, toAddr: Word): Unit = { def visitUFPField(objRef: Word, iRef: Word, toAddr: Word): Unit = {
relocsMap.get(iRef).foreach { symbol => if (automagicReloc) {
// by symbol relocsMap.get(iRef).foreach { symbol =>
val fieldOffset = iRef - objRef // by symbol
val reloc = FieldRelocRecord(num, fieldOffset, AS_UPTR, TO_SYM, 0, 0, symbol) val fieldOffset = iRef - objRef
group.relocRecs += reloc val reloc = FieldRelocRecord(num, fieldOffset, AS_UPTR, TO_SYM, 0, 0, symbol)
logger.debug("External ufuncptr relocation: %d 0x%x -> %s".format(iRef, iRef, symbol)) group.relocRecs += reloc
logger.debug("External ufuncptr relocation: %d 0x%x -> %s".format(iRef, iRef, symbol))
}
} }
} }
......
...@@ -16,6 +16,8 @@ import uvm.refimpl.MuUFPValue ...@@ -16,6 +16,8 @@ import uvm.refimpl.MuUFPValue
class BootImageWriterTest extends UvmBundleTesterBase with ExtraMatchers { class BootImageWriterTest extends UvmBundleTesterBase with ExtraMatchers {
preloadBundles("tests/uvm-refimpl-test/transitive-closure.uir") preloadBundles("tests/uvm-refimpl-test/transitive-closure.uir")
preloadHails("tests/uvm-refimpl-test/transitive-closure.hail") preloadHails("tests/uvm-refimpl-test/transitive-closure.hail")
override def makeMicroVM = MicroVM(new VMConf(automagicReloc = true))
{ {
tryWithResource(microVM.newContext()) { ctx => tryWithResource(microVM.newContext()) { ctx =>
...@@ -49,6 +51,7 @@ class BootImageWriterTest extends UvmBundleTesterBase with ExtraMatchers { ...@@ -49,6 +51,7 @@ class BootImageWriterTest extends UvmBundleTesterBase with ExtraMatchers {
tryWithResource(microVM.newContext()) { ctx => tryWithResource(microVM.newContext()) { ctx =>
val h_gs3 = ctx.handleFromGlobal("@gs3") val h_gs3 = ctx.handleFromGlobal("@gs3")
val h_gs3_1 = ctx.getFieldIRef(h_gs3, 1)
val h_gs3_2 = ctx.getFieldIRef(h_gs3, 2) val h_gs3_2 = ctx.getFieldIRef(h_gs3, 2)
val h_gs3_3 = ctx.getFieldIRef(h_gs3, 3) val h_gs3_3 = ctx.getFieldIRef(h_gs3, 3)
...@@ -75,10 +78,15 @@ class BootImageWriterTest extends UvmBundleTesterBase with ExtraMatchers { ...@@ -75,10 +78,15 @@ class BootImageWriterTest extends UvmBundleTesterBase with ExtraMatchers {
microVM.globalBundle.allNs("@gd").id shouldEqual anotherMicroVM.globalBundle.allNs("@gd").id microVM.globalBundle.allNs("@gd").id shouldEqual anotherMicroVM.globalBundle.allNs("@gd").id
tryWithResource(anotherMicroVM.newContext()) { ctx => tryWithResource(anotherMicroVM.newContext()) { ctx =>
//val h_gr1 = ctx.handleFromGlobal("@gr1")
//val h_gr1_ptr = ctx.getAddr(h_gr1)
val h_gs = ctx.handleFromGlobal("@gs") val h_gs = ctx.handleFromGlobal("@gs")
val h_gs_2 = ctx.getFieldIRef(h_gs, 2) val h_gs_2 = ctx.getFieldIRef(h_gs, 2)
val h_gs_2_ptr = ctx.getAddr(h_gs_2) val h_gs_2_ptr = ctx.getAddr(h_gs_2)
val h_gs3 = ctx.handleFromGlobal("@gs3") val h_gs3 = ctx.handleFromGlobal("@gs3")
val h_gs3_1 = ctx.getFieldIRef(h_gs3, 1)
val h_gs3_1_val = ctx.load(MemoryOrder.NOT_ATOMIC, h_gs3_1).asInstanceOf[MuUPtrValue]
val h_gs3_2 = ctx.getFieldIRef(h_gs3, 2) val h_gs3_2 = ctx.getFieldIRef(h_gs3, 2)
val h_gs3_2_ptr = ctx.getAddr(h_gs3_2) val h_gs3_2_ptr = ctx.getAddr(h_gs3_2)
val h_gs3_2_val = ctx.load(MemoryOrder.NOT_ATOMIC, h_gs3_2).asInstanceOf[MuUPtrValue] val h_gs3_2_val = ctx.load(MemoryOrder.NOT_ATOMIC, h_gs3_2).asInstanceOf[MuUPtrValue]
...@@ -87,7 +95,9 @@ class BootImageWriterTest extends UvmBundleTesterBase with ExtraMatchers { ...@@ -87,7 +95,9 @@ class BootImageWriterTest extends UvmBundleTesterBase with ExtraMatchers {
val h_gt = ctx.handleFromGlobal("@gt") val h_gt = ctx.handleFromGlobal("@gt")
val h_gt_val = ctx.load(MemoryOrder.NOT_ATOMIC, h_gt).asInstanceOf[MuUPtrValue] val h_gt_val = ctx.load(MemoryOrder.NOT_ATOMIC, h_gt).asInstanceOf[MuUPtrValue]
//val gr1_ptr = ctx.handleToPtr(h_gr1_ptr)
val gs_2_ptr = ctx.handleToPtr(h_gs_2_ptr) val gs_2_ptr = ctx.handleToPtr(h_gs_2_ptr)
val gs3_1_val = ctx.handleToPtr(h_gs3_1_val)
val gs3_2_ptr = ctx.handleToPtr(h_gs3_2_ptr) val gs3_2_ptr = ctx.handleToPtr(h_gs3_2_ptr)
val gs3_2_val = ctx.handleToPtr(h_gs3_2_val) val gs3_2_val = ctx.handleToPtr(h_gs3_2_val)
val gs3_3_val = ctx.handleToFP(h_gs3_3_val) val gs3_3_val = ctx.handleToFP(h_gs3_3_val)
......
...@@ -13,4 +13,3 @@ ...@@ -13,4 +13,3 @@
.init @gr2 = &@gr1 .init @gr2 = &@gr1
.init @gs3[0] = 43 .init @gs3[0] = 43
.init @gs3[1] = 44
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment