...
 
Commits (2)
......@@ -17,6 +17,10 @@ class BundleConstructor(idNameMap: Map[MuID, MuName], nodeList: Seq[IRBuilderNod
def findNode[T <: IRBuilderNode](id: MuID): T = {
idNodeMap.getOrElse(id, {
val maybeName = idNameMap.get(id)
println("idNodeMap:")
println(idNodeMap)
println("idNameMap:")
println(idNameMap)
throw new NodeIDNotFoundException(id, maybeName)
}).asInstanceOf[T]
}
......
......@@ -30,8 +30,8 @@ import uvm.refimpl.cmdline.NativeArgv
object MicroVM {
val logger = Logger(LoggerFactory.getLogger(getClass.getName))
val DEFAULT_SOS_SIZE: Word = 2L * 1024L * 1024L; // 2MiB
val DEFAULT_LOS_SIZE: Word = 2L * 1024L * 1024L; // 2MiB
val DEFAULT_SOS_SIZE: Word = 16L * 1024L * 1024L; // 16MiB
val DEFAULT_LOS_SIZE: Word = 16L * 1024L * 1024L; // 16MiB
val DEFAULT_GLOBAL_SIZE: Word = 1L * 1024L * 1024L; // 1MiB
val DEFAULT_STACK_SIZE: Word = 63L * 1024L; // 60KiB per stack
......
......@@ -367,11 +367,14 @@ class MuCtx(val ctxID: MuInternalID, _mutator: Mutator)(
MemoryOperations.load(ptr, uty, addr, nb)
print("Loading: " + nb + "\n")
addHandle(MuValue(uty, nb))
}
/** Store to a location. */
def store(ord: MemoryOrder, loc: MuIRefValue, newVal: MuValue): Unit = {
print("Storing: " + newVal + "\n")
val (ptr, ty) = loc.ty match {
case TypeIRef(t) => (false, t)
}
......
......@@ -13,6 +13,7 @@ import uvm.ssavariables._
import uvm.ssavariables.AtomicRMWOptr._
import uvm.types._
import uvm.refimpl.nat.NativeMemoryAccessHelper
import InterpreterThread.logger
object OpHelper {
......@@ -252,6 +253,7 @@ object PrimOpHelpers {
if (op2v == 0) throw new UvmDivisionByZeroException(ctx + "Division by zero.")
}
logger.debug("op1: " + op1v + " op2: " + op2v)
up(op match {
case BinOptr.ADD => pu(op1v) + pu(op2v)
case BinOptr.SUB => pu(op1v) - pu(op2v)
......@@ -318,6 +320,7 @@ object PrimOpHelpers {
def pu(v: BigInt): BigInt = OpHelper.prepareUnsigned(v, l)
def ps(v: BigInt): BigInt = OpHelper.prepareSigned(v, l)
logger.debug("op1: " + op1v + " op2: " + op2v)
op match {
case CmpOptr.EQ => pu(op1v) == pu(op2v)
case CmpOptr.NE => pu(op1v) != pu(op2v)
......
......@@ -3,6 +3,7 @@ package uvm.refimpl.mem
import uvm._
import uvm.refimpl._
import uvm.refimpl.integerize._
import uvm.refimpl.itpr.InterpreterThread.logger
import uvm.refimpl.nat.NativeSupport
import uvm.ssavariables.AtomicRMWOptr._
......@@ -40,7 +41,8 @@ class MemorySupport(val muMemorySize: Word) extends AutoCloseable {
def loadByte(addr: Word, inMu: Boolean = true): Byte = { assertInMuMemory(inMu, addr); theMemory.getByte(addr) }
def loadShort(addr: Word, inMu: Boolean = true): Short = { assertInMuMemory(inMu, addr); theMemory.getShort(addr) }
def loadInt(addr: Word, inMu: Boolean = true): Int = { assertInMuMemory(inMu, addr); theMemory.getInt(addr) }
def loadLong(addr: Word, inMu: Boolean = true): Long = { assertInMuMemory(inMu, addr); theMemory.getLong(addr) }
def loadLong(addr: Word, inMu: Boolean = true): Long = { assertInMuMemory(inMu, addr); val v = theMemory.getLong(addr);
logger.debug("Loaded: " + v); v}
def loadI128(addr: Word, inMu: Boolean = true): (Long, Long) = { assertInMuMemory(inMu, addr); (theMemory.getLong(addr), theMemory.getLong(addr + 8)) }
def loadFloat(addr: Word, inMu: Boolean = true): Float = { assertInMuMemory(inMu, addr); theMemory.getFloat(addr) }
def loadDouble(addr: Word, inMu: Boolean = true): Double = { assertInMuMemory(inMu, addr); theMemory.getDouble(addr) }
......@@ -48,7 +50,8 @@ class MemorySupport(val muMemorySize: Word) extends AutoCloseable {
def storeByte(addr: Word, v: Byte, inMu: Boolean = true): Unit = { assertInMuMemory(inMu, addr); theMemory.putByte(addr, v) }
def storeShort(addr: Word, v: Short, inMu: Boolean = true): Unit = { assertInMuMemory(inMu, addr); theMemory.putShort(addr, v) }
def storeInt(addr: Word, v: Int, inMu: Boolean = true): Unit = { assertInMuMemory(inMu, addr); theMemory.putInt(addr, v) }
def storeLong(addr: Word, v: Long, inMu: Boolean = true): Unit = { assertInMuMemory(inMu, addr); theMemory.putLong(addr, v) }
def storeLong(addr: Word, v: Long, inMu: Boolean = true): Unit = { assertInMuMemory(inMu, addr); theMemory.putLong(addr, v);
logger.debug("Stored: " + v) }
def storeI128(addr: Word, v: (Long, Long), inMu: Boolean = true): Unit = { assertInMuMemory(inMu, addr); val (low, high) = v; theMemory.putLong(addr, low); theMemory.putLong(addr + 8, high) }
def storeFloat(addr: Word, v: Float, inMu: Boolean = true): Unit = { assertInMuMemory(inMu, addr); theMemory.putFloat(addr, v) }
def storeDouble(addr: Word, v: Double, inMu: Boolean = true): Unit = { assertInMuMemory(inMu, addr); theMemory.putDouble(addr, v) }
......
......@@ -32,7 +32,7 @@ object SimpleImmixSpace {
private val LINE_SIZE = 128L
private val N_BUCKETS = 256
private val N_BUCKETS = 1024
}
class SimpleImmixSpace(val heap: SimpleImmixHeap, name: String, begin: Word, extend: Word)(
......
......@@ -317,6 +317,7 @@ class NativeCallHelper {
BoxPointer(rv)
}
}
logger.debug("CCALL: Returned: " + b)
Some(b)
}
}
......
......@@ -504,7 +504,7 @@ class BundleChecker {
}
if (!(i.op2.inferredType shallowEq i.opndTy)) {
throw errorFBI(s"RHS ${i.op1} has type ${i.op1.inferredType}, which does not match the operand type ${i.opndTy}")
throw errorFBI(s"RHS ${i.op2} has type ${i.op2.inferredType}, which does not match the operand type ${i.opndTy}")
}
val nResults = i.results.length
......@@ -568,7 +568,7 @@ class BundleChecker {
}
if (!(i.op2.inferredType shallowEq i.opndTy)) {
throw errorFBI(s"RHS ${i.op1} has type ${i.op1.inferredType}, which does not match the operand type ${i.opndTy}")
throw errorFBI(s"RHS ${i.op2} has type ${i.op2.inferredType}, which does not match the operand type ${i.opndTy}")
}
}
case i: FixedAlloc => { // NEW, ALLOCA
......@@ -605,7 +605,14 @@ class BundleChecker {
}
}
case i: InstGetFieldIRef => {
checkPtrAndOpnd(i.ptr, i.opnd.inferredType)
try {
checkPtrAndOpnd(i.ptr, i.opnd.inferredType)
} catch {
case fbi: StaticCheckingException => {
println(s"The operand was: ${i.opnd}")
throw fbi
}
}
i.referentTy match {
case _: AbstractStructType =>
case ty => {
......