Skip to content
GitLab
Projects Groups Snippets
  • /
  • Help
    • Help
    • Support
    • Community forum
    • Submit feedback
    • Contribute to GitLab
  • Sign in
  • M mu-impl-fast
  • Project information
    • Project information
    • Activity
    • Labels
    • Members
  • Repository
    • Repository
    • Files
    • Commits
    • Branches
    • Tags
    • Contributors
    • Graph
    • Compare
  • Issues 40
    • Issues 40
    • List
    • Boards
    • Service Desk
    • Milestones
  • Merge requests 1
    • Merge requests 1
  • Deployments
    • Deployments
    • Releases
  • Packages and registries
    • Packages and registries
    • Container Registry
  • Monitor
    • Monitor
    • Incidents
  • Analytics
    • Analytics
    • Value stream
    • Repository
  • Activity
  • Graph
  • Create a new issue
  • Commits
  • Issue Boards
Collapse sidebar

GitLab will continue to be upgraded on 7 Feb 2023 from 2.00 pm (AEDT) to 3.00 pm (AEDT). During the update, GitLab and Mattermost services will not be available. If you have any concerns with this, please talk to us at N110 (b) CSIT building.

  • mumu
  • mu-impl-fast
  • Issues
  • #90
Closed
Open
Issue created Oct 19, 2017 by Yi Lin@u4776528Owner

Register allocation with special registers

My register allocator currently deals with special registers in the following way:

  1. special registers are not usable, thus it cannot be assigned to a temporary.
  2. coalescing will not combine special registers with temporaries (even if it is safe and optimal to do so)

We can make this cleaner by manipulating interferences with special registers, and let register allocator make the decision:

  • make special registers alive at function exit, so it conflicts with all other temporaries, and register allocator won't assign it to any of the temporaries. But coalescing may combine temporaries with special registers if possible.
  • to prevent coalescing in some cases, such as
mov SP -> t
add t, 8 -> t

we cannot coalesce SP with t. Otherwise changing t will also change the stack pointer. For a general case,

OP t, v -> u

if t cannot be coalesced with special register S, the instruction selector can generate code

mov t -> t0 (with def S)
OP t0, v -> u

this will add an interference edge between t0 and S, and prevent the coalescing.

Assignee
Assign to
Time tracking